公开(公告)号：US09952769B2

公开(公告)日：2018-04-24

申请号：US15141771

申请日：2016-04-28

Applicant: Microsoft Technology Licensing, LLC

Inventor： Anirudh Badam ,  Bikash Sharma ,  Laura Marie Caulfield ,  Badriddine Khessib ,  Suman Kumar Nath ,  Jian Huang

IPC: G06F13/00 ,  G06F3/06 ,  G11C16/10 ,  G11C16/26 ,  G11C16/14 ,  G06F12/10 ,  G11B20/12

CPC classification number: G06F3/0605 ,  G06F3/061 ,  G06F3/0614 ,  G06F3/0616 ,  G06F3/0632 ,  G06F3/0638 ,  G06F3/064 ,  G06F3/0643 ,  G06F3/0659 ,  G06F3/0673 ,  G06F3/0685 ,  G06F12/10 ,  G06F2212/1016 ,  G06F2212/1036 ,  G11B20/1217 ,  G11B2020/1238 ,  G11B2020/1292 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26

Abstract: Operations of a variety of components of a storage system stack are redefined to make the system more efficient when the underlying media has a “multi-log” type interface such as the case with NAND flash SSD memory or shingled magnetic recording media. The responsibilities of components of the storage system stack are modified such that each responsibility is performed at the most efficient component (level of abstraction) of the storage stack.

公开(公告)号：US20180046576A1

公开(公告)日：2018-02-15

申请号：US15234982

申请日：2016-08-11

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Gregg B. Lesartre ,  Harvey Ray

IPC: G06F12/0802

CPC classification number: G06F12/0893 ,  G06F12/0246 ,  G06F2212/1036 ,  G06F2212/60 ,  G06F2212/7211 ,  Y02D10/13

Abstract: In one example in accordance with the present disclosure, a system may include a wear level handler to start a current rotation of a wear level algorithm through a plurality of cache line addresses in a region of memory and a location storer to store a rotation count of the rotation. The system may also include a data mover to move a cache line from the selected cache line address to a gap cache line address corresponding to the additional cache line address and a metadata setter to set a metadata of the gap cache line address to a value corresponding to the current rotation. The system may also include a current position determiner to determine, based on the value of at least one metadata and the rotation count, a current position of the current rotation after a power loss event.

公开(公告)号：US09891844B2

公开(公告)日：2018-02-13

申请号：US15485158

申请日：2017-04-11

Applicant: SanDisk Technologies LLC

Inventor： Navneeth Kankani ,  Linh Tien Truong

IPC: G06F12/12 ,  G06F3/06 ,  G06F12/02

CPC classification number: G06F3/0616 ,  G06F3/0629 ,  G06F3/0634 ,  G06F3/0638 ,  G06F3/0653 ,  G06F3/0688 ,  G06F12/0246 ,  G06F2212/1036 ,  G06F2212/1044 ,  G06F2212/7204

Abstract: Systems, methods, and/or devices are used to implement variable bit encoding to improve device endurance and extend life of storage devices. In some embodiments, the method includes determining a current endurance metric for a plurality of non-volatile memory portions configured to store data encoded in a first encoding format and determining an estimated endurance metric for the plurality of non-volatile memory portions (e.g., corresponding to estimated endurance after reconfiguration of the one or more portions to store data encoded in a second encoding format), and in accordance with a determination that reconfiguration criteria are satisfied (e.g., the estimated endurance metric comprises an improvement over the current endurance metric), reconfiguring the one or more portions to store data encoded in the second encoding format.

公开(公告)号：US09875813B2

公开(公告)日：2018-01-23

申请号：US15194447

申请日：2016-06-27

Applicant: Conor Maurice Ryan

Inventor： Conor Maurice Ryan ,  Joseph Sullivan

IPC: G06F12/00 ,  G11C29/52 ,  G11C16/34 ,  G06F3/06 ,  G06F13/24 ,  G06F12/02

CPC classification number: G11C29/52 ,  G06F3/0605 ,  G06F3/061 ,  G06F3/0616 ,  G06F3/0634 ,  G06F3/064 ,  G06F3/0649 ,  G06F3/0653 ,  G06F3/0655 ,  G06F3/0659 ,  G06F3/0664 ,  G06F3/0679 ,  G06F3/0688 ,  G06F12/0246 ,  G06F12/1009 ,  G06F13/24 ,  G06F2212/1036 ,  G06F2212/2022 ,  G06F2212/7201 ,  G06F2212/7211 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C16/349 ,  G11C29/36 ,  G11C29/38 ,  G11C29/44 ,  G11C29/50012

Abstract: The present invention includes embodiments of systems and methods for increasing the operational efficiency and extending the estimated operational lifetime of a flash memory storage device (and its component flash memory chips, LUNs and blocks of flash memory) by monitoring the health of the device and its components and, in response, adaptively tuning the operating parameters of flash memory chips during their operational lifetime, as well as employing other less extreme preventive measures in the interim, via an interface that avoids the need for direct access to the test modes of the flash memory chips. In an offline characterization phase, “test chips” from a batch of recently manufactured flash memory chips are used to simulate various usage scenarios and measure the performance effects of writing and attempting to recover (read) test patterns written with different sets of operating parameters over time (simulating desired retention periods).

公开(公告)号：US20170357571A1

公开(公告)日：2017-12-14

申请号：US15495900

申请日：2017-04-24

Applicant: Western Digital Technologies, Inc.

Inventor： Kamyar SOURI ,  Andrew J. Tomlin ,  Dmitry S. Obukhov ,  Jing Booth ,  Mei-Man L. Syu

IPC: G06F12/02

CPC classification number: G06F12/0246 ,  G06F12/0253 ,  G06F2212/1016 ,  G06F2212/1036 ,  G06F2212/7205 ,  G06F2212/7211

Abstract: Disclosed embodiments are directed to systems and methods for assigning and selecting memory units for internal memory operations in data storage systems. The embodiments can improve the efficiency of garbage collection operations by directing dynamic data into memory units with a relatively lower P/E count, directing static and system data into memory units with a relatively higher P/E count, and not mixing static and dynamic data by packing static data into separate memory units from dynamic data. In one embodiment, after completion of garbage collection of blocks, the blocks are each assigned to one of a cool down list and an available memory unit list based on a size limit of the cool down list and a number of program-erase (P/E) operations performed on each block. The blocks are subsequently selected from the lists for write operations according to whether write data includes static or dynamic data.

公开(公告)号：US20170329522A1

公开(公告)日：2017-11-16

申请号：US15527781

申请日：2014-12-31

Applicant: Shannon Systems Ltd.

Inventor： Xueshi YANG

IPC: G06F3/06 ,  G06F12/02 ,  G06F12/06

CPC classification number: G06F3/064 ,  G06F3/0616 ,  G06F3/0688 ,  G06F11/1076 ,  G06F12/0253 ,  G06F12/06 ,  G06F2212/1036 ,  G06F2212/2022 ,  G06F2212/2024 ,  G06F2212/262 ,  G06F2212/7201 ,  G06F2212/7205

Abstract: “A RAID system and method based on a solid-state storage medium. The system includes a plurality of solid-state storage devices and a main control unit. Each solid-state storage device includes a solid-state storage medium and a controller for controlling reading and writing of the solid-state storage medium. The main control unit is electrically connected to the controller of each of the solid-state storage devices in a RAID array. The main control unit is used for performing address mapping from a logical block address in the RAID array to a physical block address of the flash memory solid-state storage device. The address mapping and the RAID function can be integrated to solve the problems of write amplification and low performance. The unified management of address mapping of the solid-state storage devices can be implemented to improve the efficiency of garbage collection and wear leveling of the solid-state storage system.”

公开(公告)号：US20170315931A1

公开(公告)日：2017-11-02

申请号：US15651862

申请日：2017-07-17

Applicant: Huawei Technologies Co., Ltd.

Inventor： Duo Liu ,  Zili Shao ,  Linbo Long

IPC: G06F12/122

CPC classification number: G06F12/122 ,  G06F12/02 ,  G06F12/0246 ,  G06F2212/1036 ,  G06F2212/251 ,  G06F2212/7208

Abstract: A method for processing a memory page in memory, where the memory page in the memory includes an idle single-level cell (SLC) memory page, an active SLC memory page, an inactive SLC memory page, and a multi-level cell (MLC) memory page, and when a quantity of idle SLC memory pages of any virtual machine (VM) is less than a specified threshold, the processing method includes converting one idle SLC memory page to two MLC memory pages, copying data in two inactive SLC memory pages to the two converted MLC memory pages, and releasing storage space of the two inactive SLC memory pages to obtain two idle SLC memory pages.

公开(公告)号：US20170300423A1

公开(公告)日：2017-10-19

申请号：US15098668

申请日：2016-04-14

Applicant: Western Digital Technologies, Inc.

Inventor： Md Kamruzzaman

IPC: G06F12/10 ,  G06F12/02

CPC classification number: G06F12/109 ,  G06F12/0238 ,  G06F12/0253 ,  G06F2212/1028 ,  G06F2212/1036 ,  G06F2212/656 ,  G06F2212/657 ,  G06F2212/7201 ,  G06F2212/7205 ,  G06F2212/7208 ,  G06F2212/7211 ,  G11C16/08 ,  G11C16/349 ,  G11C16/3495

Abstract: A system may include a plurality of memory cells and a processor. The plurality of memory cells may include a plurality of physical locations at which data is stored. The processor may be configured to determine whether to swap physical locations of data stored at logical block addresses in the first logical block address collection and physical locations of data stored at logical block addresses in the second logical block address collection. The processor may be further configured to, in response to determining to swap the physical locations of the data, swap the physical locations of the data stored at the logical block addresses in the first logical block address collection and the physical locations of the data stored at the logical block addresses in the second logical block address collection.

公开(公告)号：US20170300408A1

公开(公告)日：2017-10-19

申请号：US15356667

申请日：2016-11-21

Applicant: NXP USA, INC.

Inventor： YAOQIAO LI ,  Xinjie Chen ,  Xiaoxiang Geng ,  Jian Zhou

IPC: G06F12/02 ,  G11C16/34 ,  G11C16/16 ,  G11C16/10 ,  G06F13/16 ,  G11C16/28 ,  G06F3/06

CPC classification number: G06F12/0246 ,  G06F3/0616 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0679 ,  G06F3/0688 ,  G06F13/1678 ,  G06F13/1694 ,  G06F2212/1036 ,  G06F2212/7211 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C16/28 ,  G11C16/3495

Abstract: A system for reducing stress on a memory device that has multiple memory blocks. The system includes a counting unit for incrementing count values respectively associated with the memory blocks. Each of the count values indicates the number of times the associated memory block has been erased. A controller monitors the count values. Upon detecting that a count value associated with a first memory block reaches a predefined threshold, the controller selects a second memory block from the memory blocks to be swapped with the first memory block based on a count value associated with the second memory block.

公开(公告)号：US09792054B2

公开(公告)日：2017-10-17

申请号：US15076629

申请日：2016-03-21

Applicant: International Business Machines Corporation

Inventor： Holloway H. Frost ,  Daniel E. Scheel

IPC: G06F12/00 ,  G06F3/06 ,  G06F12/06 ,  G06F12/02

CPC classification number: G06F3/0616 ,  G06F3/061 ,  G06F3/0631 ,  G06F3/0655 ,  G06F3/0659 ,  G06F3/067 ,  G06F3/0679 ,  G06F3/068 ,  G06F12/00 ,  G06F12/02 ,  G06F12/0638 ,  G06F2212/1036 ,  G06F2212/154 ,  G06F2212/214 ,  G06F2212/261 ,  G06F2212/70 ,  G06F2212/7202

Abstract: Methods and apparatuses for optimizing the performance of a storage system comprise a FLASH storage system, a hard drive storage system, and a storage controller. The storage controller is adapted to receive READ and WRITE requests from an external host, and is coupled to the FLASH storage system and the hard drive storage system. The storage controller receives a WRITE request from an external host containing data and an address, forwards the received WRITE request to the FLASH storage system and associates the address provided in the WRITE request with a selected alternative address, and provides an alternative WRITE request, including the selected alternative address and the data received in the WRITE request, to the hard drive storage system, wherein the alternative address is selected to promote sequential WRITE operations within the hard drive storage system.