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    INTERCONNECT STRUCTURE AND METHOD OF FORMING THE SAME
    22.
    发明申请
    INTERCONNECT STRUCTURE AND METHOD OF FORMING THE SAME 有权
    互连结构及其形成方法

    公开(公告)号：US20150294937A1

    公开(公告)日：2015-10-15

    申请号：US14250234

    申请日：2014-04-10

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Chien-Chih Chiu ,  Ming-Chung Liang

    IPC: H01L23/522 ,  H01L23/532 ,  H01L21/768 ,  H01L23/528

    CPC classification number: H01L23/5226 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76844 ,  H01L21/76877 ,  H01L23/528 ,  H01L23/53204 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a low-k (LK) dielectric layer over a substrate; a first conductive feature in the LK dielectric layer, wherein the first conductive feature has a first sidewall, a second sidewall facing the first sidewall, and a first bottom surface contacting the LK dielectric layer; a first dielectric feature along an upper portion of the first sidewall, wherein a length of the first dielectric feature is at least 10 percent less than a length of the first sidewall; and a second dielectric feature along an upper portion of the second sidewall. The interconnect structure may also include a second conductive feature adjacent to the first conductive feature in the LK dielectric layer.

    Abstract translation: 公开了互连结构和形成互连结构的方法。 互连结构包括在衬底上的低k（LK）电介质层; LK介电层中的第一导电特征，其中所述第一导电特征具有第一侧壁，面对所述第一侧壁的第二侧壁和与所述LK介电层接触的第一底表面; 沿着所述第一侧壁的上部的第一电介质特征，其中所述第一电介质特征的长度比所述第一侧壁的长度小至少10％; 以及沿着第二侧壁的上部的第二介电特征。 互连结构还可以包括与LK介电层中的第一导电特征相邻的第二导电特征。

    SEMICONDUCTOR DEVICE HAVING GROOVE-SHAPED VIA-HOLE
    25.
    发明申请
    SEMICONDUCTOR DEVICE HAVING GROOVE-SHAPED VIA-HOLE 有权
    具有沟槽形状的通孔的半导体器件

    公开(公告)号：US20140291864A1

    公开(公告)日：2014-10-02

    申请号：US14304225

    申请日：2014-06-13

    Applicant: FUJITSU SEMICONDUCTOR LIMITED

    Inventor： Kenichi Watanabe

    IPC: H01L23/522

    CPC classification number: H01L21/76877 ,  H01L21/76804 ,  H01L21/76843 ,  H01L23/481 ,  H01L23/485 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/5227 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53204 ,  H01L23/53223 ,  H01L23/53228 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295 ,  H01L23/562 ,  H01L23/58 ,  H01L23/585 ,  H01L29/0607 ,  H01L29/0611 ,  H01L29/0619 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a having a pattern bent at a right angle; and buried conductors 70, 72a buried in the hole-shaped via-hole 60 and the groove-shaped via-hole 66a. A groove-shaped via-hole 66a is formed to have a width which is smaller than a width of the hole-shaped via-hole 66. Defective filling of the buried conductor and the cracking of the inter-layer insulating film can be prevented. Steps on the conductor plug can be reduced. Accordingly, defective contact with the upper interconnection layer and the problems taking place in forming films can be prevented.

    Abstract translation: 半导体器件具有形成在衬底10上的绝缘膜40,42; 埋置在绝缘膜40,42的至少表面侧的互连件58; 绝缘膜60,62形成在绝缘膜42上并且包括孔形通孔60和具有以直角弯曲的图案的槽形通孔66a; 以及埋入孔形通孔60和槽形通孔66a中的埋入导体70,72a。 形成沟槽状的通孔66a的宽度小于孔状通孔66的宽度。可以防止埋入导体的填充不充分和层间绝缘膜的开裂。 导体插头上的步骤可以减少。 因此，可以防止与上部互连层的不良接触以及在形成膜中发生的问题。

    Passivation Scheme
    30.
    发明申请
    Passivation Scheme 审中-公开
    钝化计划

    公开(公告)号：US20140246772A1

    公开(公告)日：2014-09-04

    申请号：US14276702

    申请日：2014-05-13

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    Inventor： Hsien-Wei Chen

    IPC: H01L23/498 ,  H01L23/532

    CPC classification number: H01L23/49811 ,  H01L21/31058 ,  H01L21/76802 ,  H01L21/76828 ,  H01L21/76831 ,  H01L23/53204 ,  H01L23/53295 ,  H01L2224/13

    Abstract: An integrated circuit includes a conductive pad disposed over a substrate. A first passivation layer is disposed over the conductive pad. A second passivation layer is disposed over the first passivation layer. A stress buffer layer is disposed over the second passivation layer. A conductive interconnect layer is over and coupled to the conductive pad and over the stress buffer layer with the conductive interconnect layer adjoining sidewalls of the first passivation layer and the stress buffer layer.

    Abstract translation: 集成电路包括设置在基板上的导电焊盘。 第一钝化层设置在导电焊盘的上方。 第二钝化层设置在第一钝化层上。 应力缓冲层设置在第二钝化层上。 导电互连层在导电焊盘之上和耦合到应力缓冲层上，导电互连层邻接第一钝化层和应力缓冲层的侧壁。

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