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公开(公告)号：US20240266942A1
公开(公告)日：2024-08-08
申请号：US18481563
申请日：2023-10-05
Applicant: Chicony Electronics Co., Ltd.
Inventor： Ming-Jang Yang
CPC classification number: H02M1/08 , H02J7/0063 , H02J7/007182 , H02M3/156 , H03K3/037 , H03K5/00 , H03K2005/00078
Abstract: A control device, a control signal generation method and a voltage conversion device are provided. A delay circuit generates a delay signal based on a power signal. An output end of a logic circuit outputs a third level voltage in response to that the power signal or the battery signal is at a second level voltage. The output end outputs a fourth level voltage in response to that the power signal and the battery signal both are at a first level voltage. In response to that an output signal of the output end is the third level voltage, an output circuit outputs a level voltage of the received power signal when the delay signal is changed from the first level voltage to the second level voltage. The output circuit outputs a stopping voltage in response to that the output signal of the logic circuit is the fourth level voltage.
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公开(公告)号：US12057765B2
公开(公告)日：2024-08-06
申请号：US17707329
申请日：2022-03-29
Applicant: Renesas Electronics America Inc.
Inventor： Mengmeng Du , Matthew Alan Grant , Daniel Dahua Zheng
Abstract: Apparatuses and methods for operating a power converter are described. An integrated circuit can be integrated in a high-side driver of a high-side fiend-effect transistor (FET) of the power converter. The integrated circuit can detect a phase node voltage of a power integrated circuit. The integrated circuit can, in response to the phase node voltage being less than a threshold voltage, operate a high-side FET of the power integrated circuit in a constant-current mode. The integrated circuit can, in response to the phase node voltage being greater than the threshold voltage, operate the high-side FET of the power integrated circuit in a constant-voltage mode.
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23.发明公开公开(公告)号：US20240258900A1
公开(公告)日：2024-08-01
申请号：US18516906
申请日：2023-11-21
Applicant: ARK MICROELECTRONIC CORP. LTD.
Inventor： Yi-Lun Shen , Yu-Yun Huang
Abstract: A control circuit of a power conversion circuit includes an energy storing circuit coupled between an AC/DC rectifier circuit and a DC/DC conversion circuit. When a first condition “the absolute peak value of the input voltage of the AC/DC rectifying circuit is smaller than a reference voltage” is satisfied, discharge current is provided for lowering the voltage on the first output end of the AC/DC rectifying circuit. When the first condition and a second condition “the discharge current is smaller than reference current” are both satisfied, a switch of the energy storing circuit is turned on. When the first condition and the second are not both satisfied, the switch of the energy storing circuit is turned off.
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公开(公告)号：US12047006B2
公开(公告)日：2024-07-23
申请号：US17531812
申请日：2021-11-22
Applicant: Ark Semiconductor Corp. Ltd.
Inventor： Yi-Lun Shen , Jian-Heng Guo
CPC classification number: H02M3/33569 , H02M1/08
Abstract: A flyback converter includes a primary winding, a main switch, a charging switch, a primary side controller and an energy storage device. The primary winding receives an input power; the primary side controller has a power input terminal and provides a first control signal and a second control signal to the main switch and the charging switch; after the main switch is turned off, the charging switch maintains turned on during a charging period. During the charging period, the input power passes through the primary winding and the charging switch, and stores a first portion of the input power in the energy storage device as a power supply energy; the power input terminal is coupled to the energy storage device, and the primary side controller receives the power supply power from the energy storage device through the power input terminal.
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公开(公告)号：US20240243666A1
公开(公告)日：2024-07-18
申请号：US18409868
申请日：2024-01-11
Applicant: Takeshi SATO , Minoru KADO
Inventor： Takeshi SATO , Minoru KADO
CPC classification number: H02M3/33569 , H02M1/08
Abstract: A switching power supply device includes a secondary-side control circuit including a switching control circuit that generates a voltage for ON-OFF control of a switching element for synchronous rectification. The secondary-side control circuit includes an external terminal to which a drain voltage of the switching element is input, a power supply terminal to which a voltage rectified by the switching element is input, a peak hold circuit that holds a peak of the drain voltage input to the external terminal, and an abnormality detection circuit that operates based on the voltage at the power supply terminal or a voltage derived from the voltage at the power supply terminal and a holding voltage of the peak hold circuit, and outputs an abnormality detection signal when detecting an abnormal state in which the voltage at the power supply terminal decreases or no voltage is input to the power supply terminal.
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Patent Agency Ranking
公开(公告)号：US20240243665A1
公开(公告)日：2024-07-18
申请号：US18156055
申请日：2023-01-18
Applicant: Monolithic Power Systems, Inc.
Inventor： Vipin Pala
CPC classification number: H02M3/33507 , H02M1/08
Abstract: A composite switch circuit having a normally-on power switch device and a normally-off power switch device in cascode configuration is discussed. The composite switch circuit is with reduced power loss by biasing a common connection of the source terminal of the normally-on power switch device and the drain terminal of the normally-off power switch device with a low voltage supply during a reverse recovery process of the composite switch circuit.
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公开(公告)号：US20240243658A1
公开(公告)日：2024-07-18
申请号：US18521225
申请日：2023-11-28
Applicant: FUJI ELECTRIC CO., LTD.
Inventor： Ryuji YAMADA
IPC: H02M3/155 , G01R19/175 , H02M1/08 , H03K5/24
CPC classification number: H02M3/155 , G01R19/175 , H02M1/08 , H03K5/24
Abstract: A current detection circuit for a power supply circuit configured to generate an output voltage from an input voltage thereof, the power supply circuit including an inductor configured to receive the input voltage, a transistor configured to control an inductor current flowing through the inductor, and a diode coupled to a first node that is a node at which the inductor and the transistor are coupled. The current detection circuit is configured to detect the inductor current, and includes: a first capacitor coupled to the first node; and a second capacitor provided between the first capacitor and a ground, the second capacitor being coupled in series with the first capacitor.
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公开(公告)号：US12040725B2
公开(公告)日：2024-07-16
申请号：US17911419
申请日：2020-04-10
Applicant: Mitsubishi Electric Corporation
Inventor： Shota Hanioka , Masahiro Iezawa
IPC: H02M7/5387 , H02M1/00 , H02M1/08 , H02M1/38 , H02P27/06
CPC classification number: H02M7/5387 , H02M1/0009 , H02M1/08 , H02M1/385 , H02P27/06
Abstract: A power conversion device includes a switching signal generation unit that generates switching signals so that time points of at least one of pairs synchronize with each other. A first pair includes a rising time point at a first junction point of a first single-phase leg, and a falling time point at a second junction point of a second single-phase leg. A second pair includes a falling time point at the first junction point and a rising time point at the second junction point. The switching signal generation unit determines time points to turn on or turn off for upper arm switching element and a lower arm switching element based on phase currents respectively at a rising time point and at a falling time point of the terminal voltages.
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公开(公告)号：US12040720B2
公开(公告)日：2024-07-16
申请号：US17704442
申请日：2022-03-25
Inventor： Yen-Shin Lai , Yong-Yi Huang , Xiang-Yu Wu , You-Quan Dong , Shu-Hao Wu
CPC classification number: H02M3/33573 , H02M1/0035 , H02M1/08 , H02M3/01 , H02M3/33576
Abstract: A resonance conversion device and a universal serial bus circuit are provided. The resonance conversion device includes an input filter circuit, a full-bridge LLC converter circuit, a transformer circuit, a rectifier filter circuit, and a controller. The controller is configured to determine whether an indication voltage of a voltage command is less than or equal to a threshold value and to perform the following steps: in response to the indication voltage being less than or equal to the threshold value, controlling the full-bridge LLC converter circuit into a half-bridge operation mode, and regulating the DC output voltage by performing half-bridge burst mode control on the full-bridge LLC converter circuit based on the DC output voltage; and in response to the indication voltage being greater than the threshold value, regulating the DC output voltage by performing full-bridge burst mode control on the full-bridge LLC converter circuit based on the DC output voltage.
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公开(公告)号：US12033922B2
公开(公告)日：2024-07-09
申请号：US17557138
申请日：2021-12-21
Applicant: DENSO CORPORATION
Inventor： Akihiro Fukatsu , Noboru Nagase , Toshihiro Nagaya
IPC: H01L23/495 , H01L23/00 , H01L23/31 , H01L25/07 , H01L25/16 , H02M1/08 , H02M7/537 , H02P27/06 , H05K1/18
CPC classification number: H01L23/49537 , H01L23/49575 , H01L25/072 , H01L25/162 , H02M1/08 , H02M7/537 , H05K1/181 , H01L23/3121 , H01L23/49513 , H01L24/32 , H01L24/37 , H01L24/40 , H01L24/48 , H01L24/73 , H01L2224/32245 , H01L2224/37147 , H01L2224/3716 , H01L2224/40175 , H01L2224/40499 , H01L2224/48245 , H01L2224/73221 , H01L2224/73263 , H01L2924/01029 , H01L2924/01047 , H01L2924/0105 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/10272 , H01L2924/13055 , H01L2924/13091 , H01L2924/1433 , H02P27/06 , H05K2201/10015 , H05K2201/10166
Abstract: A semiconductor device includes: first and second semiconductor elements each having two electrodes respectively disposed on two surfaces; two first terminals respectively connected to the two electrodes of the first semiconductor element and arranged side by side in one direction; two second terminals respectively connected to the two electrodes of the second semiconductor element, and arranged side by side in the one direction to be adjacent to the two first terminals; and a sealing resin portion covering the first and second semiconductor elements and the first and second terminals in a state where facing surfaces of the first and second terminals are exposed from the sealing resin portion. The facing surfaces of the two first terminals have different area ratios, the facing surfaces of the two second terminals have different area ratios, and one of the first terminals is arranged adjacent to both the two second terminals.
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