公开(公告)号：US11837582B2

公开(公告)日：2023-12-05

申请号：US18148327

申请日：2022-12-29

Applicant: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.

Inventor： Guilian Gao ,  Cyprian Emeka Uzoh ,  Jeremy Alfred Theil ,  Belgacem Haba ,  Rajesh Katkar

IPC: H01L25/065 ,  H01L21/768 ,  H01L23/538 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L21/76898 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/95

Abstract: Dies and/or wafers are stacked and bonded in various arrangements including stacks, and may be covered with a molding to facilitate handling, packaging, and the like. In various examples, the molding may cover more or less of a stack, to facilitate connectivity with the devices of the stack, to enhance thermal management, and so forth.

公开(公告)号：US11817409B2

公开(公告)日：2023-11-14

申请号：US17563506

申请日：2021-12-28

Applicant: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.

Inventor： Belgacem Haba ,  Rajesh Katkar ,  Ilyas Mohammed ,  Javier A. DeLaCruz

IPC: H01L23/00 ,  H01L21/78

CPC classification number: H01L24/08 ,  H01L21/78 ,  H01L24/80 ,  H01L24/94 ,  H01L2224/08146 ,  H01L2224/80006 ,  H01L2224/80895 ,  H01L2224/80896

Abstract: A bonded structure can include a first reconstituted element comprising a first element and having a first side comprising a first bonding surface and a second side opposite the first side. The first reconstituted element can comprise a first protective material disposed about a first sidewall surface of the first element. The bonded structure can comprise a second reconstituted element comprising a second element and having a first side comprising a second bonding surface and a second side opposite the first side. The first reconstituted element can comprise a second protective material disposed about a second sidewall surface of the second element. The second bonding surface of the first side of the second reconstituted element can be directly bonded to the first bonding surface of the first side of the first reconstituted element without an intervening adhesive along a bonding interface.

公开(公告)号：US20230360950A1

公开(公告)日：2023-11-09

申请号：US17662180

申请日：2022-05-05

Applicant: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.

Inventor： Guilian Gao

IPC: H01L21/683 ,  H01L23/00

CPC classification number: H01L21/6838 ,  H01L21/6833 ,  H01L24/80 ,  H01L21/6836 ,  H01L2221/68327 ,  H01L2221/68368 ,  H01L2224/8018 ,  H01L2224/8082 ,  H01L2224/80896 ,  H01L2224/80905 ,  H01L2224/80009 ,  H01L24/08 ,  H01L2224/08225 ,  H01L24/05 ,  H01L2224/05647

Abstract: Embodiments of various systems, methods, and devices for gang flipping and individual picking dies are disclosed. The embodiments disclosed herein may be used, for example, in the manufacture of directly bonded devices.

公开(公告)号：US11791307B2

公开(公告)日：2023-10-17

申请号：US17209638

申请日：2021-03-23

Applicant: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.

Inventor： Chandrasekhar Mandalapu ,  Gaius Gillman Fountain, Jr. ,  Guilian Gao

IPC: H01L21/683 ,  H01L21/78 ,  H01L25/065 ,  H01L23/00

CPC classification number: H01L24/83 ,  H01L21/6836 ,  H01L21/78 ,  H01L24/03 ,  H01L24/08 ,  H01L24/09 ,  H01L24/32 ,  H01L24/33 ,  H01L24/98 ,  H01L2221/68327 ,  H01L2221/68368 ,  H01L2221/68381 ,  H01L2224/03002 ,  H01L2224/08145 ,  H01L2224/09181 ,  H01L2224/32145 ,  H01L2224/33181 ,  H01L2224/80895 ,  H01L2224/83009 ,  H01L2224/83896 ,  H01L2224/83948

Abstract: Devices and techniques include process steps for preparing various microelectronic components for bonding, such as for direct bonding without adhesive. The processes include providing a first bonding surface on a first surface of the microelectronic components, bonding a handle to the prepared first bonding surface, and processing a second surface of the microelectronic components while the microelectronic components are gripped at the handle. In some embodiments, the processes include removing the handle from the first bonding surface, and directly bonding the microelectronic components at the first bonding surface to other microelectronic components.

公开(公告)号：US11762200B2

公开(公告)日：2023-09-19

申请号：US17124408

申请日：2020-12-16

Applicant: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.

Inventor： Rajesh Katkar ,  Belgacem Haba

IPC: G02B27/01 ,  G02B27/14 ,  H01L25/07 ,  G02B27/10 ,  H01L25/075

CPC classification number: G02B27/0172 ,  G02B27/102 ,  G02B27/141 ,  H01L25/0753 ,  G02B2027/0178

Abstract: A bonded optical device is disclosed. The bonded optical device can include a first optical element, a second optical element, and an optical pathway. The first optical element has a first array of optical emitters configured to emit light of a first color. The first optical element is bonded to at least one processor element, the at least one processor element including active circuitry configured to control operation of the first optical element. The second optical element has a second array of optical emitters configured to emit light of a second color different from the first color. The second optical element is bonded to the at least one processor element. The optical pathway is optically coupled with the first and second optical elements. The optical pathway is configured to transmit a superposition of light from the first and second optical emitters to an optical output to be viewed by users.

公开(公告)号：US11735523B2

公开(公告)日：2023-08-22

申请号：US17314555

申请日：2021-05-07

Applicant: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.

Inventor： Cyprian Emeka Uzoh

IPC: H01L21/00 ,  H01L23/528 ,  H01L21/768

CPC classification number: H01L23/528 ,  H01L21/76898

Abstract: Techniques are employed to mitigate the anchoring effects of cavity sidewall adhesion on an embedded conductive interconnect structure, and to allow a lower annealing temperature to be used to join opposing conductive interconnect structures. A vertical gap may be disposed between the conductive material of an embedded interconnect structure and the sidewall of the cavity to laterally unpin the conductive structure and allow uniaxial expansion of the conductive material. Additionally or alternatively, one or more vertical gaps may be disposed within the bonding layer, near the embedded interconnect structure to laterally unpin the conductive structure and allow uniaxial expansion of the conductive material.

公开(公告)号：US20230207514A1

公开(公告)日：2023-06-29

申请号：US18069783

申请日：2022-12-21

Applicant: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.

Inventor： Guilian Gao ,  Gaius Gillman Fountain, JR. ,  Cyprian Emeka Uzoh ,  Thomas Workman

IPC: H01L23/00 ,  H01L21/67 ,  H01L21/683

CPC classification number: H01L24/80 ,  H01L21/67144 ,  H01L21/6838 ,  H01L21/6831 ,  H01L24/74 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/74

Abstract: A system for direct bonding can include a substrate support configured to hold a substrate for direct bonding and a die handling tool including an end effector configured to hold a die and bring the die into contact with the substrate supported on the substrate support, the end effector configured to initiate contact between the substrate and a bond initiation region of the die and to subsequently allow contact between the substrate and other regions of the die.

公开(公告)号：US20230207437A1

公开(公告)日：2023-06-29

申请号：US18052399

申请日：2022-11-03

Applicant: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.

Inventor： Belgacem Haba

IPC: H01L23/498 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L23/49827 ,  H01L24/08 ,  H01L24/32 ,  H01L24/33 ,  H01L25/0657 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2224/08145 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/14511

Abstract: A stacked electronic device is disclosed. The stacked electronic device can comprise a first stacked assembly including a first plurality of integrated device dies. The first plurality of integrated device dies can comprise a first integrated device die. A second stacked assembly is disposed over the first stacked assembly. The second stacked assembly includes a second plurality of device dies, and the second plurality of device dies can comprise a second integrated device die. A first channel can extend at least partially through the first stacked assembly. The first integrated device die can comprise a first circuit, and the first channel is connected to the first circuit. A second channel can extend through and bypass the first stacked assembly, the second channel extending at least partially through the second stacked assembly. The second integrated device die can comprise a second circuit, and the second channel is connected to the second circuit.

公开(公告)号：US20230197560A1

公开(公告)日：2023-06-22

申请号：US18067668

申请日：2022-12-16

Applicant: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.

Inventor： Rajesh Katkar ,  Belgacem Haba

IPC: H01L23/38 ,  H01L23/00

CPC classification number: H01L23/38 ,  H01L24/08 ,  H01L2224/08245 ,  H01L2924/351

Abstract: In some aspects, the disclosed technology provides microelectronic devices which can effectively dissipate heat and manage hot spot. In some embodiments, a disclosed microelectronic device may include a substrate having a thickness in a first direction and at least one thermoelectric unit disposed in or on the substrate. The thermoelectric unit may be configured to transfer heat along a second lateral direction orthogonal to the first direction.

公开(公告)号：US20230187398A1

公开(公告)日：2023-06-15

申请号：US18147375

申请日：2022-12-28

Applicant: Adeia Semiconductor Bonding Technologies Inc.

Inventor： Guilian GAO ,  Javier A. DELACRUZ ,  Shaowu HUANG ,  Liang WANG ,  Gaius Giliman FOUNTAIN, JR. ,  Rajesh KATKAR ,  Cyprian Emeka UZOH

IPC: H01L23/00

CPC classification number: H01L24/08 ,  H01L24/05 ,  H01L24/06 ,  H01L24/74 ,  H01L24/80 ,  H01L24/89 ,  H01L2224/05557 ,  H01L2224/06131 ,  H01L2224/06177 ,  H01L2224/8013 ,  H01L2224/08147 ,  H01L2224/80007 ,  H01L2224/80011 ,  H01L2224/80031 ,  H01L2224/80047 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/3512

Abstract: Structures and techniques provide bond enhancement in microelectronics by trapping contaminants and byproducts during bonding processes, and arresting cracks. Example bonding surfaces are provided with recesses, sinks, traps, or cavities to capture small particles and gaseous byproducts of bonding that would otherwise create detrimental voids between microscale surfaces being joined, and to arrest cracks. Such random voids would compromise bond integrity and electrical conductivity of interconnects being bonded. In example systems, a predesigned recess space or predesigned pattern of recesses placed in the bonding interface captures particles and gases, reducing the formation of random voids, thereby improving and protecting the bond as it forms. The recess space or pattern of recesses may be placed where particles collect on the bonding surface, through example methods of determining where mobilized particles move during bond wave propagation. A recess may be repeated in a stepped reticule pattern at the wafer level, for example, or placed by an aligner or alignment process.