中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

43 records (took 0.016 seconds)

    SEMICONDUCTOR MEMORY DEVICES
    31.
    发明申请
    SEMICONDUCTOR MEMORY DEVICES 有权
    半导体存储器件

    公开(公告)号：US20140126265A1

    公开(公告)日：2014-05-08

    申请号：US14055061

    申请日：2013-10-16

    Applicant: Jaekyu LEE ,  Changkyu KIM

    Inventor： Jaekyu LEE ,  Changkyu KIM

    IPC: G11C5/06

    CPC classification number: G11C5/063 ,  G11C7/18 ,  G11C13/0002 ,  G11C2213/82 ,  H01L27/0207 ,  H01L27/228 ,  H01L27/2436 ,  H01L43/08 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/143 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147

    Abstract: Semiconductor memory devices include unit cells two-dimensionally arranged along rows and columns in one cell array block. The unit cells are classified into a plurality of cell subgroups, and each of the cell subgroups includes the unit cells constituting a plurality of the rows. Each of the unit cells includes a selection element and a data storage part. A word line is connected to gate electrodes of selection elements of the unit cells constituting each column. Bit lines are connected to data storage parts of the unit cells constituting the rows. A source line, parallel to the bit line, is electrically connected to source terminals of the selection elements of the unit cells in each cell subgroup. The source line is parallel to the bit line. A distance between the source line and the select bit line is equal to a distance between the bit lines adjacent to each other.

    Abstract translation: 半导体存储器件包括在一个单元阵列块中沿行和列二维排列的单位单元。 单元单元被分类为多个单元子组，并且每个单元子组包括构成多行的单元单元。 每个单位单元包括选择单元和数据存储单元。 字线连接到构成每列的单元电池的选择元件的栅电极。 位线连接到构成行的单位单元的数据存储部分。 平行于位线的源极线电连接到每个电池子组中的单元电池的选择元件的源极端子。 源极线与位线平行。 源极线和选择位线之间的距离等于彼此相邻的位线之间的距离。

    Cache and/or socket sensitive multi-processor cores breadth-first traversal
    33.
    发明授权
    Cache and/or socket sensitive multi-processor cores breadth-first traversal 有权
    缓存和/或套接字敏感的多处理器核宽度优先遍历

    公开(公告)号：US08533432B2

    公开(公告)日：2013-09-10

    申请号：US13629087

    申请日：2012-09-27

    Applicant: Nadathur Rajagopalan Satish ,  Changkyu Kim ,  Jatin Chhugani ,  Jason D. Sewall

    Inventor： Nadathur Rajagopalan Satish ,  Changkyu Kim ,  Jatin Chhugani ,  Jason D. Sewall

    IPC: G06F9/38 ,  G06F9/06 ,  G06F15/80 ,  G06F13/14

    CPC classification number: G06F9/52

    Abstract: Methods, apparatuses and storage device associated with cache and/or socket sensitive breadth-first iterative traversal of a graph by parallel threads, are described. A vertices visited array (VIS) may be employed to track graph vertices visited. VIS may be partitioned into VIS sub-arrays, taking into consideration cache sizes of LLC, to reduce likelihood of evictions. Potential boundary vertices arrays (PBV) may be employed to store potential boundary vertices for a next iteration, for vertices being visited in a current iteration. The number of PBV generated for each thread may take into consideration a number of sockets, over which the processor cores employed are distributed. The threads may be load balanced; further data locality awareness to reduce inter-socket communication may be considered, and/or lock-and-atomic free update operations may be employed.

    Abstract translation: 描述了通过并行线程与缓存和/或套接字敏感的宽度优先遍历遍历图形的方法，装置和存储装置。 可以使用顶点访问阵列（VIS）来跟踪所访问的图形顶点。 VIS可以分为VIS子阵列，考虑到LLC的缓存大小，以减少驱逐的可能性。 可以使用潜在边界顶点阵列（PBV）来存储用于下一次迭代的潜在边界顶点，用于在当前迭代中被访问的顶点。 为每个线程生成的PBV的数量可以考虑多个套接字，所采用的处理器核在其上分布。 螺纹可以是负载平衡的; 可以考虑进一步的数据局部性意识以减少套接字间通信，和/或可以采用锁定和无原子的更新操作。

    Shared cache memories for multi-core processors
    34.
    发明授权
    Shared cache memories for multi-core processors 有权
    用于多核处理器的共享高速缓存

    公开(公告)号：US08417891B2

    公开(公告)日：2013-04-09

    申请号：US12335381

    申请日：2008-12-15

    Applicant: Wenlong Li ,  Yu Chen ,  Changkyu Kim ,  Christopher J. Hughes ,  Yen-Kuang Chen

    Inventor： Wenlong Li ,  Yu Chen ,  Changkyu Kim ,  Christopher J. Hughes ,  Yen-Kuang Chen

    IPC: G06F12/00

    CPC classification number: G06F12/084 ,  G06F12/0815

    Abstract: Embodiments of shared cache memories for multi-core processors are presented. In one embodiment, a cache memory comprises a group of sampling cache sets and a controller to determine a number of misses that occur in the group of sampling cache sets. The controller is operable to determine a victim cache line for a cache set based at least in part on the number of misses.

    Abstract translation: 呈现用于多核处理器的共享高速缓冲存储器的实施例。 在一个实施例中，高速缓存存储器包括一组采样高速缓存组和控制器，用于确定在采样高速缓存组组中出现的多少个未命中。 控制器可操作以至少部分地基于错失次数来确定用于高速缓存组的受害者高速缓存行。

    CACHE AND/OR SOCKET SENSITIVE MULTI-PROCESSOR CORES BREADTH-FIRST TRAVERSAL
    35.
    发明申请
    CACHE AND/OR SOCKET SENSITIVE MULTI-PROCESSOR CORES BREADTH-FIRST TRAVERSAL 有权
    高速缓存和/或插座敏感多处理器最初的第一个TRAVERSAL

    公开(公告)号：US20130086354A1

    公开(公告)日：2013-04-04

    申请号：US13629087

    申请日：2012-09-27

    Applicant: Nadathur Rajagopalan Satish ,  Changkyu Kim ,  Jatin Chhuagani ,  Jason D. Sewall

    Inventor： Nadathur Rajagopalan Satish ,  Changkyu Kim ,  Jatin Chhuagani ,  Jason D. Sewall

    IPC: G06F15/80

    CPC classification number: G06F9/52

    Abstract: Methods, apparatuses and storage device associated with cache and/or socket sensitive breadth-first iterative traversal of a graph by parallel threads, are disclosed. In embodiments, a vertices visited array (VIS) may be employed to track graph vertices visited. VIS may be partitioned into VIS sub-arrays, taking into consideration cache sizes of LLC, to reduce likelihood of evictions. In embodiments, potential boundary vertices arrays (PBV) may be employed to store potential boundary vertices for a next iteration, for vertices being visited in a current iteration. The number of PBV generated for each thread may take into consideration a number of sockets, over which the processor cores employed are distributed. In various embodiments, the threads may be load balanced; further data locality awareness to reduce inter-socket communication may be considered, and/or lock-and-atomic free update operations may be employed. Other embodiments may be disclosed or claimed.

    Abstract translation: 公开了通过并行线程与缓存和/或套接字敏感的宽度优先遍历遍历图形的方法，装置和存储装置。 在实施例中，可以采用顶点访问阵列（VIS）来跟踪所访问的图形顶点。 VIS可以分为VIS子阵列，考虑到LLC的缓存大小，以减少驱逐的可能性。 在实施例中，可以采用潜在边界顶点阵列（PBV）来存储针对当前迭代中被访问的顶点的下一次迭代的潜在边界顶点。 为每个线程生成的PBV的数量可以考虑多个套接字，所采用的处理器核在其上分布。 在各种实施例中，螺纹可以是负载平衡的; 可以考虑进一步的数据局部性意识以减少套接字间通信，和/或可以采用锁定和无原子的更新操作。 可以公开或要求保护其他实施例。

    Parallel operation in B+ trees
    39.
    发明授权
    Parallel operation in B+ trees 有权
    平行操作在B +树

    公开(公告)号：US09405782B2

    公开(公告)日：2016-08-02

    申请号：US13996508

    申请日：2011-08-29

    Applicant: Jason D. Sewall ,  Changkyu Kim ,  Jatin Chhugani ,  Nadathur Rajagopalan Satish

    Inventor： Jason D. Sewall ,  Changkyu Kim ,  Jatin Chhugani ,  Nadathur Rajagopalan Satish

    IPC: G06F17/30 ,  G06F9/50

    CPC classification number: G06F17/30327 ,  G06F9/5005 ,  G06F2209/5018

    Abstract: Embodiments of techniques and systems for parallel processing of B+ trees are described. A parallel B+ tree processing module with partitioning and redistribution may include a set of threads executing a batch of B+ tree operations on a B+ tree in parallel. The batch of operations may be partitioned amongst the threads. Next, a search may be performed to determine which leaf nodes in the B+ tree are to be affected by which operations. Then, the threads may redistribute operations between each other such that multiple threads will not operate on the same leaf node. The threads may then perform B+ tree operations on the leaf nodes of the B+ tree in parallel. Subsequent modifications to nodes in the B+ may similarly be redistributed and performed in parallel as the threads work up the tree.

    Abstract translation: 描述了用于B +树的并行处理的技术和系统的实施例。 具有分区和再分配的并行B +树处理模块可以包括一组在B +树上并行执行一批B +树操作的线程。 该批操作可以在线程之间划分。 接下来，可以执行搜索以确定B +树中的哪些叶节点将受哪些操作影响。 然后，线程可以在彼此之间重新分配操作，使得多个线程将不在同一叶节点上操作。 然后，线程可以并行地在B +树的叶节点上执行B +树操作。 当线程处理树时，对B +中的节点的后续修改可以类似地重新分布并且并行执行。

Patent Agency Ranking