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    COMPUTER KEYBOARD PROVIDED WITH THUMB-OPERATED OPTICAL MOUSE
    1.
    发明公开
    COMPUTER KEYBOARD PROVIDED WITH THUMB-OPERATED OPTICAL MOUSE 审中-公开

    公开(公告)号：US20240241588A1

    公开(公告)日：2024-07-18

    申请号：US18562383

    申请日：2022-06-15

    Applicant: Jaekyu LEE

    Inventor： Jaekyu LEE

    IPC: G06F3/02 ,  G06F3/03 ,  G06F3/0354

    CPC classification number: G06F3/0213 ,  G06F3/0308 ,  G06F3/03543

    Abstract: The present invention relates to a computer keyboard provided with an optical mouse (light mouse) used with a thumb, for improving the inconvenience of moving between a keyboard and a mouse when using a computer, wherein while both hands remain positioned on the computer keyboard, the thumb of one hand may move a mouse pointer and the thumb of the other hand may perform a clicking operation, and the clicking operation can also be performed using the index finger, the middle finger, and the ring finger of the hand that moves the mouse pointer.

    High density semiconductor memory devices
    4.
    发明授权
    High density semiconductor memory devices 有权
    高密度半导体存储器件

    公开(公告)号：US09082468B2

    公开(公告)日：2015-07-14

    申请号：US13692157

    申请日：2012-12-03

    Applicant: Jaekyu Lee ,  Youngmin Kang ,  Hyunju Lee

    Inventor： Jaekyu Lee ,  Youngmin Kang ,  Hyunju Lee

    IPC: G11C8/00 ,  G11C8/10 ,  G11C11/16 ,  G11C8/08

    CPC classification number: G11C8/10 ,  G11C8/08 ,  G11C11/16 ,  G11C11/1653 ,  G11C11/1659

    Abstract: High density semiconductor memory devices are provided. The device may include a cell array region including a lower structure, an upper structure, and a selection structure, the selection structure being interposed between the lower and upper structures and including word lines, and a decoding circuit controlling voltages applied to the word lines. The decoding circuit may be configured to apply a first voltage to a pair of the word lines adjacent to each other and to apply a second voltage different from the first voltage to the remaining ones of the word lines, in response to word line address information input thereto.

    Abstract translation: 提供了高密度半导体存储器件。 该装置可以包括包括下部结构，上部结构和选择结构的单元阵列区域，所述选择结构插入在下部结构和上部结构之间并且包括字线，以及解码电路，其控制施加到字线的电压。 解码电路可以被配置为响应于字线地址信息输入，向彼此相邻的一对字线施加第一电压并且向剩余的字线施加不同于第一电压的第二电压 到此。

    Semiconductor memory devices
    6.
    发明授权
    Semiconductor memory devices 有权
    半导体存储器件

    公开(公告)号：US09299392B2

    公开(公告)日：2016-03-29

    申请号：US14055061

    申请日：2013-10-16

    Applicant: Jaekyu Lee ,  Changkyu Kim

    Inventor： Jaekyu Lee ,  Changkyu Kim

    IPC: G11C5/06 ,  H01L27/105 ,  G11C13/00 ,  H01L27/02 ,  H01L27/22 ,  H01L43/08 ,  H01L45/00 ,  H01L27/24 ,  G11C7/18

    CPC classification number: G11C5/063 ,  G11C7/18 ,  G11C13/0002 ,  G11C2213/82 ,  H01L27/0207 ,  H01L27/228 ,  H01L27/2436 ,  H01L43/08 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/143 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147

    Abstract: Semiconductor memory devices include unit cells two-dimensionally arranged along rows and columns in one cell array block. The unit cells are classified into a plurality of cell subgroups, and each of the cell subgroups includes the unit cells constituting a plurality of the rows. Each of the unit cells includes a selection element and a data storage part. A word line is connected to gate electrodes of selection elements of the unit cells constituting each column. Bit lines are connected to data storage parts of the unit cells constituting the rows. A source line, parallel to the bit line, is electrically connected to source terminals of the selection elements of the unit cells in each cell subgroup. The source line is parallel to the bit line. A distance between the source line and the select bit line is equal to a distance between the bit lines adjacent to each other.

    Abstract translation: 半导体存储器件包括在一个单元阵列块中沿行和列二维排列的单位单元。 单元单元被分类为多个单元子组，并且每个单元子组包括构成多行的单元单元。 每个单位单元包括选择单元和数据存储单元。 字线连接到构成每列的单元电池的选择元件的栅电极。 位线连接到构成行的单位单元的数据存储部分。 平行于位线的源极线电连接到每个电池子组中的单元电池的选择元件的源极端子。 源极线与位线平行。 源极线和选择位线之间的距离等于彼此相邻的位线之间的距离。

    SEMICONDUCTOR MEMORY DEVICES
    8.
    发明申请
    SEMICONDUCTOR MEMORY DEVICES 有权
    半导体存储器件

    公开(公告)号：US20140126265A1

    公开(公告)日：2014-05-08

    申请号：US14055061

    申请日：2013-10-16

    Applicant: Jaekyu LEE ,  Changkyu KIM

    Inventor： Jaekyu LEE ,  Changkyu KIM

    IPC: G11C5/06

    CPC classification number: G11C5/063 ,  G11C7/18 ,  G11C13/0002 ,  G11C2213/82 ,  H01L27/0207 ,  H01L27/228 ,  H01L27/2436 ,  H01L43/08 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/143 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147

    Abstract: Semiconductor memory devices include unit cells two-dimensionally arranged along rows and columns in one cell array block. The unit cells are classified into a plurality of cell subgroups, and each of the cell subgroups includes the unit cells constituting a plurality of the rows. Each of the unit cells includes a selection element and a data storage part. A word line is connected to gate electrodes of selection elements of the unit cells constituting each column. Bit lines are connected to data storage parts of the unit cells constituting the rows. A source line, parallel to the bit line, is electrically connected to source terminals of the selection elements of the unit cells in each cell subgroup. The source line is parallel to the bit line. A distance between the source line and the select bit line is equal to a distance between the bit lines adjacent to each other.

    Abstract translation: 半导体存储器件包括在一个单元阵列块中沿行和列二维排列的单位单元。 单元单元被分类为多个单元子组，并且每个单元子组包括构成多行的单元单元。 每个单位单元包括选择单元和数据存储单元。 字线连接到构成每列的单元电池的选择元件的栅电极。 位线连接到构成行的单位单元的数据存储部分。 平行于位线的源极线电连接到每个电池子组中的单元电池的选择元件的源极端子。 源极线与位线平行。 源极线和选择位线之间的距离等于彼此相邻的位线之间的距离。

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