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    OPTOELECTRONIC MEMORY DEVICES
    31.
    发明申请
    OPTOELECTRONIC MEMORY DEVICES 有权
    光电存储器件

    公开(公告)号：US20100290264A1

    公开(公告)日：2010-11-18

    申请号：US12842158

    申请日：2010-07-23

    Applicant: Fen Chen ,  Richard Steven Kontra ,  Tom C. Lee ,  Theodore M. Levin ,  Christopher David Muzzy ,  Timothy Dooling Sullivan

    Inventor： Fen Chen ,  Richard Steven Kontra ,  Tom C. Lee ,  Theodore M. Levin ,  Christopher David Muzzy ,  Timothy Dooling Sullivan

    IPC: G11C13/04 ,  G11C11/00

    CPC classification number: G11C13/0009 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/04 ,  G11C13/047 ,  G11C2013/0054 ,  H01L45/1213 ,  H01L45/145

    Abstract: A structure. The structure includes a substrate, a resistive/reflective region on the substrate, and a light source/light detecting and/or a sens-amp circuit configured to ascertain a reflectance and/or resistance change in the resistive/reflective region. The resistive/reflective region includes a material having a characteristic of the material's reflectance and/or resistance being changed due to a phase change in the material. The resistive/reflective region is configured to respond, to an electric current through the resistive/reflective region and/or a laser beam projected on the resistive/reflective region, by the phase change in the material which causes a reflectance and/resistance change in the resistive/reflective region from a first reflectance and/or resistance value to a second reflectance and/or resistance value different from the first reflectance and/or resistance value.

    Abstract translation: 一个结构。 该结构包括衬底，衬底上的电阻/反射区域以及被配置为确定电阻/反射区域中的反射率和/或电阻变化的光源/光检测和/或感测放大器电路。 电阻/反射区域包括具有材料的反射率和/或电阻的特性的材料由于材料的相变而改变。 电阻/反射区域被配置为通过材料的相变来响应通过电阻/反射区域的电流和/或投射在电阻/反射区域上的激光束，这导致反射和/ 电阻/反射区域从第一反射率和/或电阻值到不同于第一反射率和/或电阻值的第二反射率和/或电阻值。

    Semiconductor chips with reduced stress from underfill at edge of chip
    32.
    发明授权
    Semiconductor chips with reduced stress from underfill at edge of chip 失效
    半导体芯片在芯片边缘的底层填料中的应力减小

    公开(公告)号：US07777339B2

    公开(公告)日：2010-08-17

    申请号：US11830228

    申请日：2007-07-30

    Applicant: Timothy Harrison Daubenspeck ,  Jeffrey Peter Gambino ,  Christopher David Muzzy ,  Wolfgang Sauter

    Inventor： Timothy Harrison Daubenspeck ,  Jeffrey Peter Gambino ,  Christopher David Muzzy ,  Wolfgang Sauter

    IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

    CPC classification number: H01L23/3192 ,  H01L21/563 ,  H01L23/3178 ,  H01L2224/73203 ,  H01L2924/01079

    Abstract: Structures and methods for forming the same. A semiconductor chip includes a semiconductor substrate and a transistor on the semiconductor substrate. The chip further includes N interconnect layers on top of the semiconductor substrate and being electrically coupled to the transistor, N being a positive integer. The chip further includes a first dielectric layer on top of the N interconnect layers, and a second dielectric layer on top of the first dielectric layer. The second dielectric layer is in direct physical contact with each interconnect layer of the N interconnect layers. The chip further includes an underfill layer on top of the second dielectric layer. The second dielectric layer is sandwiched between the first dielectric layer and the underfill layer. The chip further includes a laminate substrate on top of the underfill layer. The underfill layer is sandwiched between the second dielectric layer and the laminate substrate.

    Abstract translation: 用于形成它的结构和方法。 半导体芯片包括半导体衬底和半导体衬底上的晶体管。 该芯片还包括在半导体衬底之上的N个互连层，并且电耦合到晶体管，N是正整数。 芯片还包括在N个互连层的顶部上的第一介电层，以及在第一介电层的顶部上的第二介电层。 第二电介质层与N互连层的每个互连层直接物理接触。 芯片还包括在第二电介质层顶部的底部填充层。 第二电介质层夹在第一介电层和底部填充层之间。 芯片还包括在底部填充层顶部的层压基板。 底部填充层被夹在第二介电层和层叠基板之间。

    SEMICONDUCTOR CHIPS WITH REDUCED STRESS FROM UNDERFILL AT EDGE OF CHIP
    35.
    发明申请
    SEMICONDUCTOR CHIPS WITH REDUCED STRESS FROM UNDERFILL AT EDGE OF CHIP 失效
    具有降低应力的半导体芯片

    公开(公告)号：US20090032929A1

    公开(公告)日：2009-02-05

    申请号：US11830228

    申请日：2007-07-30

    Applicant: Timothy Harrison Daubenspeck ,  Jeffrey Peter Gambino ,  Christopher David Muzzy ,  Wolfgang Sauter

    Inventor： Timothy Harrison Daubenspeck ,  Jeffrey Peter Gambino ,  Christopher David Muzzy ,  Wolfgang Sauter

    IPC: H01L23/24 ,  H01L21/00

    CPC classification number: H01L23/3192 ,  H01L21/563 ,  H01L23/3178 ,  H01L2224/73203 ,  H01L2924/01079

    Abstract: Structures and methods for forming the same. A semiconductor chip includes a semiconductor substrate and a transistor on the semiconductor substrate. The chip further includes N interconnect layers on top of the semiconductor substrate and being electrically coupled to the transistor, N being a positive integer. The chip further includes a first dielectric layer on top of the N interconnect layers, and a second dielectric layer on top of the first dielectric layer. The second dielectric layer is in direct physical contact with each interconnect layer of the N interconnect layers. The chip further includes an underfill layer on top of the second dielectric layer. The second dielectric layer is sandwiched between the first dielectric layer and the underfill layer. The chip further includes a laminate substrate on top of the underfill layer. The underfill layer is sandwiched between the second dielectric layer and the laminate substrate.

    Abstract translation: 用于形成它的结构和方法。 半导体芯片包括半导体衬底和半导体衬底上的晶体管。 该芯片还包括在半导体衬底之上的N个互连层，并且电耦合到晶体管，N是正整数。 芯片还包括在N个互连层的顶部上的第一介电层，以及在第一介电层的顶部上的第二介电层。 第二电介质层与N互连层的每个互连层直接物理接触。 芯片还包括在第二电介质层顶部的底部填充层。 第二电介质层夹在第一介电层和底部填充层之间。 芯片还包括在底部填充层顶部的层压基板。 底部填充层被夹在第二介电层和层叠基板之间。

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