公开(公告)号：US12040305B2

公开(公告)日：2024-07-16

申请号：US18144376

申请日：2023-05-08

Applicant: Amkor Technology Singapore Holding Pte. Ltd.

Inventor： Jong Ok Chun ,  Nozad Karim ,  Richard Chen ,  Giuseppe Selli ,  Michael Kelly

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/552 ,  H01L23/66 ,  H05K1/02 ,  H05K7/10 ,  H05K1/11 ,  H05K1/16

CPC classification number: H01L24/49 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/552 ,  H01L23/66 ,  H05K1/0215 ,  H05K7/10 ,  H01L24/48 ,  H01L24/73 ,  H01L2223/6655 ,  H01L2223/6677 ,  H01L2224/04042 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/0218 ,  H05K1/115 ,  H05K1/165 ,  H05K2201/09436 ,  H05K2201/09481 ,  H05K2201/10287 ,  H01L2224/73265 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2924/00 ,  H01L2924/15311 ,  H01L2224/73265 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2924/00 ,  H01L2224/73265 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2924/15311 ,  H01L2224/73265 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/45099 ,  H01L2924/00014 ,  H01L2224/45015 ,  H01L2924/207

Abstract: An electronic component package includes a substrate and an electronic component mounted to the substrate, the electronic component including a bond pad. A first antenna terminal is electrically connected to the bond pad, the first antenna terminal being electrically connected to a second antenna terminal of the substrate. A package body encloses the electronic component, the package body having a principal surface. An antenna is formed on the principal surface by applying an electrically conductive coating. An embedded interconnect extends through the package body between the substrate and the principal surface and electrically connects the second antenna terminal to the antenna. Applying an electrically conductive coating to form the antenna is relatively simple thus minimizing the overall package manufacturing cost. Further, the antenna is relatively thin thus minimizing the overall package size.

公开(公告)号：US20180277471A1

公开(公告)日：2018-09-27

申请号：US15994006

申请日：2018-05-31

Applicant: Dai Nippon Printing Co., Ltd.

Inventor： Takamasa Takano

IPC: H01L23/498 ,  H05K1/11 ,  H05K3/42 ,  H01L21/48 ,  H01L21/768 ,  H01L23/14 ,  H01L23/00 ,  H01L23/48 ,  H05K3/44

CPC classification number: H01L23/49827 ,  H01L21/486 ,  H01L21/76898 ,  H01L23/147 ,  H01L23/481 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/49866 ,  H01L23/49894 ,  H01L24/17 ,  H01L2224/05647 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/01024 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/15747 ,  H01L2924/15786 ,  H01L2924/1579 ,  H05K1/113 ,  H05K3/426 ,  H05K3/445 ,  H05K2201/09436 ,  H05K2201/09581 ,  H05K2201/09609 ,  H05K2201/09836 ,  H05K2201/09854 ,  H05K2201/10378 ,  H05K2203/0733 ,  H05K2203/1178 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49165

Abstract: A method of manufacturing a through-hole electrode substrate includes forming a plurality of through-holes in a substrate, forming a plurality of through-hole electrodes by filling a conductive material into the plurality of through-holes, forming a first insulation layer on one surface of the substrate, forming a plurality of first openings which expose the plurality of through-hole electrodes corresponding to each of the plurality of through-hole electrodes, on the first insulation layer and correcting a position of the plurality of first openings using the relationship between a misalignment amount of a measured distance value of an open position of a leaning through-hole among the plurality of through-holes and of a design distance value of the open position of the leaning through-hole among the plurality of through-holes with respect to a center position of the substrate.

公开(公告)号：US20170148723A1

公开(公告)日：2017-05-25

申请号：US15340945

申请日：2016-11-01

Applicant: Intel Corporation

Inventor： Ravindra V. Tanikella

IPC: H01L23/498 ,  H01L23/31 ,  C08K9/10 ,  C08G73/12 ,  C08K3/36 ,  H01L23/00 ,  H01L21/48

CPC classification number: H01L23/49894 ,  C08F283/04 ,  C08G73/121 ,  C08K3/36 ,  C08K9/10 ,  C08K2201/011 ,  C08L79/08 ,  C08L2666/66 ,  H01L21/4857 ,  H01L21/563 ,  H01L23/293 ,  H01L23/295 ,  H01L23/296 ,  H01L23/3185 ,  H01L23/49822 ,  H01L23/49866 ,  H01L24/16 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0104 ,  H01L2924/01042 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07025 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15747 ,  H01L2924/15763 ,  H01L2924/15787 ,  H01L2924/15791 ,  H01L2924/18161 ,  H01L2924/351 ,  H05K1/112 ,  H05K3/28 ,  H05K3/421 ,  H05K3/422 ,  H05K3/4602 ,  H05K3/4688 ,  H05K2201/0154 ,  H05K2201/0158 ,  H05K2201/09436 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/09827 ,  H05K2203/1163 ,  H05K2203/121 ,  H01L2924/00 ,  H01L2224/0401

Abstract: Highly reliable interconnections for microelectronic packaging. In one embodiment, dielectric layers in a build-up interconnect have a gradation in glass transition temperature; and the later applied dielectric layers are laminated at temperatures lower than the glass transition temperatures of the earlier applied dielectric layers. In one embodiment, the glass transition temperatures of earlier applied dielectric films in a build-up interconnect are increased through a thermosetting process to exceed the temperature for laminating the later applied dielectric films. In one embodiment, a polyimide material is formed with embedded catalysts to promote cross-linking after a film of the polyimide material is laminated (e.g., through photo-chemical or thermal degradation of the encapsulant of the catalysts). In one embodiment, the solder resist opening walls have a wettable layer generated through laser assisted seeding so that there is no gap between the solder resist opening walls and no underfill in the solder resist opening.

公开(公告)号：US09585260B2

公开(公告)日：2017-02-28

申请号：US14260007

申请日：2014-04-23

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Jae Hyun Lim ,  Jong In Ryu ,  Sun Ho Kim ,  Eun Jung Jo ,  Kyu Hwan Oh ,  Do Jae Yoo

IPC: H05K1/11 ,  H05K3/34 ,  H05K3/28 ,  H05K3/40 ,  H01L23/00 ,  H05K3/00 ,  H05K3/32

CPC classification number: H05K3/3478 ,  H01L24/97 ,  H01L2224/16225 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/19106 ,  H05K1/111 ,  H05K1/115 ,  H05K3/0052 ,  H05K3/284 ,  H05K3/321 ,  H05K3/4015 ,  H05K2201/09409 ,  H05K2201/09436 ,  H05K2201/10318 ,  H05K2201/10424 ,  H05K2201/10787 ,  H05K2203/0228 ,  H05K2203/1316 ,  H01L2924/00012

Abstract: There are provided an electronic component module capable of increasing a degree of integration by mounting electronic components on both surfaces of a substrate, and a manufacturing method thereof. The electronic component module according to an exemplary embodiment of the present disclosure includes: a substrate; a plurality of electronic components mounted on both surfaces of the substrate; connection conductors each having one end bonded to one surface of the substrate using an conductive adhesive; and a molded portion having the connection conductor embedded therein and formed on one surface of the substrate, wherein the connection conductor may have at least one blocking member preventing a spread of the conductive adhesive.

Abstract translation: 提供一种能够通过将电子部件安装在基板的两个表面上而提高集成度的电子部件模块及其制造方法。 根据本公开的示例性实施例的电子部件模块包括：基板; 安装在所述基板的两个表面上的多个电子部件; 连接导体各自具有使用导电粘合剂结合到基板的一个表面的一端; 以及模制部分，其具有嵌入其中并且形成在基板的一个表面上的连接导体，其中连接导体可以具有防止导电粘合剂扩散的至少一个阻挡构件。

公开(公告)号：US20160329273A1

公开(公告)日：2016-11-10

申请号：US15214532

申请日：2016-07-20

Applicant: Dai Nippon Printing Co., Ltd.

Inventor： Takamasa Takano

IPC: H01L23/498 ,  H01L23/00 ,  H01L21/48

CPC classification number: H01L23/49827 ,  H01L21/486 ,  H01L21/76898 ,  H01L23/147 ,  H01L23/481 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/49866 ,  H01L23/49894 ,  H01L24/17 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/15747 ,  H01L2924/15786 ,  H01L2924/1579 ,  H05K1/113 ,  H05K3/426 ,  H05K3/445 ,  H05K2201/09436 ,  H05K2201/09581 ,  H05K2201/09609 ,  H05K2201/09836 ,  H05K2201/09854 ,  H05K2201/10378 ,  H05K2203/0733 ,  H05K2203/1178 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49165 ,  H01L2224/05647 ,  H01L2924/01024 ,  H01L2924/01079

Abstract: A method of manufacturing a through-hole electrode substrate includes forming a plurality of through-holes in a substrate, forming a plurality of through-hole electrodes by filling a conductive material into the plurality of through-holes, forming a first insulation layer on one surface of the substrate, forming a plurality of first openings which expose the plurality of through-hole electrodes corresponding to each of the plurality of through-hole electrodes, on the first insulation layer and correcting a position of the plurality of first openings using the relationship between a misalignment amount of a measured distance value of an open position of a leaning through-hole among the plurality of through-holes and of a design distance value of the open position of the leaning through-hole among the plurality of through-holes with respect to a center position of the substrate.

公开(公告)号：US20160163613A1

公开(公告)日：2016-06-09

申请号：US14900651

申请日：2014-06-24

Applicant: DENSO CORPORATION

Inventor： Shinya UCHIBORI ,  Norihisa IMAIZUMI ,  Masayuki TAKENAKA

IPC: H01L23/31 ,  H05K1/18 ,  H01L23/498

CPC classification number: H01L23/3157 ,  H01L23/3121 ,  H01L23/49811 ,  H01L23/49827 ,  H01L24/73 ,  H01L25/16 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19105 ,  H05K1/181 ,  H05K3/284 ,  H05K3/301 ,  H05K3/3415 ,  H05K2201/09436 ,  H05K2201/10462 ,  H05K2201/10515 ,  H05K2201/10537 ,  H05K2201/10583 ,  H05K2201/10757 ,  H05K2201/2036 ,  H01L2924/00012 ,  H01L2924/00

Abstract: An electronic apparatus includes a board, a first electronic component, a mold resin and a second electronic component. The board has a first surface and a second surface opposite to the first surface. The first electronic component is mounted on the first surface of the board. The mold resin seals the first electronic component and the first surface of the board. The second electronic component is arranged on the mold resin.

Abstract translation: 电子设备包括板，第一电子部件，模具树脂和第二电子部件。 板具有与第一表面相对的第一表面和第二表面。 第一电子部件安装在板的第一表面上。 模具树脂密封第一电子部件和板的第一表面。 第二电子部件布置在模制树脂上。

公开(公告)号：US20160143147A1

公开(公告)日：2016-05-19

申请号：US14923992

申请日：2015-10-27

Applicant: Samsung Electro-Mechanics Co., Ltd.

Inventor： Min Woo PARK ,  Seung Pil JUNG

IPC: H05K1/18 ,  H05K3/30 ,  H05K1/11

CPC classification number: H05K1/115 ,  H01L2224/16227 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/181 ,  H01L2924/19105 ,  H05K1/111 ,  H05K3/284 ,  H05K3/3415 ,  H05K2201/09436 ,  H05K2201/096 ,  H05K2201/09827 ,  H05K2201/09863 ,  H05K2201/10977 ,  H05K2203/1316 ,  H05K2203/1563 ,  Y02P70/611 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: The electronic device module and method thereof includes a board, an electronic device, a sealing part, and a connection conductor. The board includes external connection electrodes. The electronic device is mounted on the board. The sealing part is configured to seal the electronic device. The connection conductor is configured to penetrate through the sealing part and including one end bonded to the external connection electrodes of the board. One of the external connection electrodes includes a reinforcing via disposed in the board.

Abstract translation: 电子设备模块及其方法包括板，电子设备，密封部分和连接导体。 电路板包括外部连接电极。 电子设备安装在电路板上。 密封部件被构造成密封电子设备。 连接导体被构造成穿过密封部分并且包括结合到板的外部连接电极的一端。 外部连接电极中的一个包括设置在板中的加强通孔。

公开(公告)号：US20150223361A1

公开(公告)日：2015-08-06

申请号：US14260007

申请日：2014-04-23

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Jae Hyun LIM ,  Jong In RYU ,  Sun Ho KIM ,  Eun Jung JO ,  Kyu Hwan OH ,  Do Jae YOO

IPC: H05K7/02 ,  H05K13/04 ,  H05K3/34

CPC classification number: H05K3/3478 ,  H01L24/97 ,  H01L2224/16225 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/19106 ,  H05K1/111 ,  H05K1/115 ,  H05K3/0052 ,  H05K3/284 ,  H05K3/321 ,  H05K3/4015 ,  H05K2201/09409 ,  H05K2201/09436 ,  H05K2201/10318 ,  H05K2201/10424 ,  H05K2201/10787 ,  H05K2203/0228 ,  H05K2203/1316 ,  H01L2924/00012

Abstract: There are provided an electronic component module capable of increasing a degree of integration by mounting electronic components on both surfaces of a substrate, and a manufacturing method thereof. The electronic component module according to an exemplary embodiment of the present disclosure includes: a substrate; a plurality of electronic components mounted on both surfaces of the substrate; connection conductors each having one end bonded to one surface of the substrate using an conductive adhesive; and a molded portion having the connection conductor embedded therein and formed on one surface of the substrate, wherein the connection conductor may have at least one blocking member preventing a spread of the conductive adhesive.

Abstract translation: 提供一种能够通过将电子部件安装在基板的两个表面上而提高集成度的电子部件模块及其制造方法。 根据本公开的示例性实施例的电子部件模块包括：基板; 安装在所述基板的两个表面上的多个电子部件; 连接导体各自具有使用导电粘合剂结合到基板的一个表面的一端; 以及模制部分，其具有嵌入其中并且形成在基板的一个表面上的连接导体，其中连接导体可以具有防止导电粘合剂扩散的至少一个阻挡构件。

公开(公告)号：US08796825B2

公开(公告)日：2014-08-05

申请号：US13353217

申请日：2012-01-18

Applicant: Ravindra V. Tanikella

Inventor： Ravindra V. Tanikella

IPC: H01L23/58 ,  H01L23/12 ,  H01L23/52

CPC classification number: H01L23/49894 ,  C08F283/04 ,  C08G73/121 ,  C08K3/36 ,  C08K9/10 ,  C08K2201/011 ,  C08L79/08 ,  C08L2666/66 ,  H01L21/4857 ,  H01L21/563 ,  H01L23/293 ,  H01L23/295 ,  H01L23/296 ,  H01L23/3185 ,  H01L23/49822 ,  H01L23/49866 ,  H01L24/16 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0104 ,  H01L2924/01042 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07025 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15747 ,  H01L2924/15763 ,  H01L2924/15787 ,  H01L2924/15791 ,  H01L2924/18161 ,  H01L2924/351 ,  H05K1/112 ,  H05K3/28 ,  H05K3/421 ,  H05K3/422 ,  H05K3/4602 ,  H05K3/4688 ,  H05K2201/0154 ,  H05K2201/0158 ,  H05K2201/09436 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/09827 ,  H05K2203/1163 ,  H05K2203/121 ,  H01L2924/00 ,  H01L2224/0401

Abstract: Highly reliable interconnections for microelectronic packaging. In one embodiment, dielectric layers in a build-up interconnect have a gradation in glass transition temperature; and the later applied dielectric layers are laminated at temperatures lower than the glass transition temperatures of the earlier applied dielectric layers. In one embodiment, the glass transition temperatures of earlier applied dielectric films in a build-up interconnect are increased through a thermosetting process to exceed the temperature for laminating the later applied dielectric films. In one embodiment, a polyimide material is formed with embedded catalysts to promote cross-linking after a film of the polyimide material is laminated (e.g., through photo-chemical or thermal degradation of the encapsulant of the catalysts). In one embodiment, the solder resist opening walls have a wettable layer generated through laser assisted seeding so that there is no gap between the solder resist opening walls and no underfill in the solder resist opening.

Abstract translation: 用于微电子封装的高度可靠的互连。 在一个实施例中，积聚互连中的电介质层具有玻璃化转变温度的等级; 并且稍后施加的电介质层在低于较早施加的电介质层的玻璃化转变温度的温度下被层压。 在一个实施方案中，通过热固化工艺增加了积聚互连中早期施加的介电膜的玻璃化转变温度，以超过用于层压后来施加的电介质膜的温度。 在一个实施方案中，在层压聚酰亚胺材料的膜（例如，通过催化剂的密封剂的光化学或热降解）之后，用嵌入的催化剂形成聚酰亚胺材料以促进交联。 在一个实施例中，阻焊剂开口壁具有通过激光辅助接种产生的可湿性层，使得阻焊剂开口壁之间没有间隙，并且在阻焊剂开口中没有底部填充物。

公开(公告)号：US20140003015A1

公开(公告)日：2014-01-02

申请号：US14016707

申请日：2013-09-03

Applicant: Shinji WATANABE ,  Nobuhiro MIKAMI ,  Junya SATO ,  Kenichiro FUJII ,  Katsumi ABE ,  Atsumasa SAWADA

Inventor： Shinji WATANABE ,  Nobuhiro MIKAMI ,  Junya SATO ,  Kenichiro FUJII ,  Katsumi ABE ,  Atsumasa SAWADA

IPC: H05K1/18

CPC classification number: H05K1/18 ,  H01L24/18 ,  H01L24/24 ,  H01L24/82 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/18 ,  H01L2224/24051 ,  H01L2224/24226 ,  H01L2224/24998 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/76155 ,  H01L2224/82102 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/1515 ,  H01L2924/15151 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19103 ,  H01L2924/19104 ,  H01L2924/19105 ,  H01L2924/3011 ,  H01L2924/3511 ,  H05K1/023 ,  H05K1/0271 ,  H05K1/0284 ,  H05K1/185 ,  H05K1/189 ,  H05K3/0014 ,  H05K3/32 ,  H05K3/4644 ,  H05K2201/0187 ,  H05K2201/0191 ,  H05K2201/0195 ,  H05K2201/09018 ,  H05K2201/09036 ,  H05K2201/09045 ,  H05K2201/09118 ,  H05K2201/09436 ,  H05K2201/10477 ,  H05K2201/10515 ,  H05K2201/1053 ,  H05K2201/10636 ,  H05K2201/10734 ,  H05K2203/1469 ,  H05K2203/302 ,  Y02P70/611 ,  H01L2924/00

Abstract: An object of the present invention is to allow stress that may be applied to a semiconductor package to be suppressed, when the semiconductor package is mounted on a curved board. In a mount board 1, a semiconductor package 20 is mounted on a curved board 10 including a curved surface on at least a portion thereof. The curved board 10 includes a pedestal portion 13a disposed on a region of the curved surface portion where the semiconductor package 20 is mounted and having an upper surface thereof formed flat, and a plurality of pad portions 15a disposed on the flat surface of the pedestal portion 13a. The pedestal portion 13a is formed of an insulating material. The semiconductor package 20 is mounted on the pad portions 15a.

Abstract translation: 本发明的目的在于，当将半导体封装安装在弯曲的基板上时，可以抑制对半导体封装件施加的应力。 在安装基板1中，将半导体封装20安装在其至少一部分上包括弯曲表面的弯曲板10上。 弯曲板10包括设置在半导体封装20安装的弯曲表面部分的区域上并具有平坦的上表面的基座部分13a和设置在基座部分的平坦表面上的多个焊盘部分15a 13a。 基座部分13a由绝缘材料形成。 半导体封装20安装在焊盘部分15a上。