公开(公告)号：US20120205141A1

公开(公告)日：2012-08-16

申请号：US13345974

申请日：2012-01-09

Applicant: Taiji OGAWA ,  Hirohito WATANABE ,  Masakazu SATO

Inventor： Taiji OGAWA ,  Hirohito WATANABE ,  Masakazu SATO

IPC: H05K1/02

CPC classification number: H05K1/024 ,  H01P3/081 ,  H05K1/0225 ,  H05K1/0245 ,  H05K1/0253 ,  H05K2201/09236 ,  H05K2201/09681

Abstract: The printed wiring board has a conductor of signal line 41 and two conductive lines 42 on one face of the first insulating layer 10 covered by a second insulating layer 20, while having a ground layer of the ground 30 potential on the opposite face thereof, when the dielectric tangent A of the second insulating layer (insulating layer A) 20 is larger than the dielectric tangent B of the first insulating layer (insulating layer B) 10, Relational Expression 1: (relative permittivity B)·(width (W41) of signal line(s) 41)/(thickness (T10) of first insulating layer (insulating layer B) 10)>(relative permittivity A)·{(thickness (T41) of signal line(s) 41)/(distance (S1) between signal line(s) 41 and one conductive line 42a)+(thickness (T41) of signal line(s) 41)/(distance (S2) between signal line(s) 41 and other conductive line 42b)+(thickness (T41) of signal lines 41)/(distance (S3) between pair of signal lines (41a and 41b)·2} is satisfied.

Abstract translation: 印刷电路板具有由第二绝缘层20覆盖的第一绝缘层10的一面上的信号线41的导体和两条导线42，同时在其相对面上具有接地层30的电位的地层， 第二绝缘层（绝缘层A）20的介质切线A大于第一绝缘层（绝缘层B）10的介质切线B，关系式1（相对介电常数B）·（宽（W41） 信号线41）/（第一绝缘层（绝缘层B）的厚度（T10））10）>（相对介电常数A）·{（信号线的厚度（T41）41）/（距离（S1 信号线41和一根导线42a之间）+（信号线41的厚度（T41））/（信号线41与其他导线42b的距离（S2））+（厚度 信号线41的（T41）/（信号线对（41a，41b）·2之间的距离（S3））满足。

公开(公告)号：US20110247863A1

公开(公告)日：2011-10-13

申请号：US13077304

申请日：2011-03-31

Applicant: Hirohito WATANABE

Inventor： Hirohito WATANABE

IPC: H05K1/02 ,  H05K3/00

CPC classification number: H05K1/028 ,  H05K1/0218 ,  H05K3/1216 ,  H05K2201/0373

Abstract: [Object] To provide a flexible printed board improved in bendability.[Means for solving] The flexible printed board 2 comprises: an insulating substrate 21; a circuit wiring 22 laid on the insulating substrate 21; a circuit protection layer 23 laid on the circuit wiring 22; a shield conductive layer 24 laid on the circuit protection layer 23; and a shield insulating layer 25 laid on the shield conductive layer 24, and is characterized by meeting the following Expression (1). 0.75≦E2/E1≦1.29  Expression (1) Note that E1 denotes the tensile elastic modulus of the shield conductive layer 24 and E2 denotes the tensile elastic modulus of the shield insulating layer 25.

Abstract translation: 提供改善弯曲性的柔性印刷电路板。 [解决方案]柔性印刷电路板2包括：绝缘基板21; 布置在绝缘基板21上的电路布线22; 布置在电路布线22上的电路保护层23; 布置在电路保护层23上的屏蔽导电层24; 以及敷设在屏蔽导电层24上的屏蔽绝缘层25，其特征在于满足下述式（1）。 0.75＆nlE; E2 / E1＆nlE; 1.29表达式（1）注意，E1表示屏蔽导电层24的拉伸弹性模量，E2表示屏蔽绝缘层25的拉伸弹性模量。

公开(公告)号：US07880215B2

公开(公告)日：2011-02-01

申请号：US11667736

申请日：2005-11-16

Applicant: Hirohito Watanabe ,  Motofumi Saitou ,  Hiroshi Sunamura

Inventor： Hirohito Watanabe ,  Motofumi Saitou ,  Hiroshi Sunamura

IPC: H01L29/76 ,  H01L29/788

CPC classification number: H01L27/11534 ,  G11C16/0408 ,  G11C16/0416 ,  G11C16/10 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11526 ,  H01L29/42324 ,  H01L29/66825

Abstract: A diffusion layer (102) is formed in the surface region of a semiconductor substrate (101). A control gate electrode (103) is formed on the substrate. An interlayer dielectric film (108) covers the entire surface of the substrate. A drain leader line (104) made of a semiconductor such as n-type polysilicon is led from the drain region, and a source leader line (107) is led from the source region through the interlayer dielectric film. The drain leader line is surrounded by an annular floating gate (105). In erase, for example, the control gate is set to a ground potential, and a positive voltage is applied to the drain leader line to remove electrons in the floating gate to the drain leader line. In write, positive voltages are applied to the control gate electrode and drain leader line to generate CHE and inject hot electrons into the floating gate. This allows to thin the gate insulating film of a flash memory, increase the degree of integration of a nonvolatile memory, and lower the driving voltage.

Abstract translation: 在半导体衬底（101）的表面区域形成扩散层（102）。 在基板上形成控制栅电极（103）。 层间绝缘膜（108）覆盖基板的整个表面。 由漏极区域引出由诸如n型多晶硅的半导体制成的漏极引线（104），并且源极引线（107）从源极区域通过层间绝缘膜引出。 排水引导线被环形浮动门（105）包围。 在擦除中，例如，将控制栅极设置为接地电位，并且将正电压施加到漏极引线，以将浮动栅极中的电子去除到漏极引线。 在写入时，正电压施加到控制栅电极和漏极引线，以产生CHE并将热电子注入浮栅。 这样可以使闪存的栅极绝缘膜变薄，增加非易失性存储器的集成度，并降低驱动电压。

公开(公告)号：US20100319972A1

公开(公告)日：2010-12-23

申请号：US12820605

申请日：2010-06-22

Applicant: Hirohito WATANABE

Inventor： Hirohito WATANABE

IPC: H05K1/11 ,  H05K1/02 ,  B32B37/02 ,  B29C65/02

CPC classification number: H05K1/117 ,  H05K1/118 ,  H05K3/0058 ,  H05K3/386 ,  H05K2201/0191 ,  H05K2201/09154 ,  H05K2201/09827 ,  H05K2201/2009 ,  Y10T29/49147 ,  Y10T156/10

Abstract: A printed circuit board having a connection terminal which includes: an insulating substrate including first and second surfaces, and an end surface along an outline normal to an insertion direction of the connection terminal; at least one lead wiring layer formed on the first surface of the insulating substrate; an insulating protection film covering the lead wiring layer; at least one lead terminal layer constituting an end portion of the lead wiring layer, the lead terminal layer being formed into a strip, and having an end surface along the outline; a reinforcement body adhered on the second surface of the insulating substrate at a backside position of the lead terminal layer; wherein a distance between an outer surface of the lead terminal layer and an outer surface of the reinforcement body on the outline side is smaller than a distance therebetween on the lead wiring layer side.

Abstract translation: 一种具有连接端子的印刷电路板，包括：绝缘基板，包括第一表面和第二表面;以及沿着垂直于连接端子的插入方向的轮廓的端面; 形成在绝缘基板的第一表面上的至少一个引线布线层; 覆盖引线布线层的绝缘保护膜; 构成所述引线配线层的端部的至少一个引线端子层，所述引线端子层形成为带状，并且具有沿着所述轮廓的端面; 加强体，其在所述引线端子层的背面位置粘附在所述绝缘基板的所述第二表面上; 其中，引线端子层的外表面与轮廓侧的加强体的外表面之间的距离小于引线布线层侧的距离。

公开(公告)号：US07838945B2

公开(公告)日：2010-11-23

申请号：US12093666

申请日：2006-10-18

Applicant: Motofumi Saitoh ,  Hirohito Watanabe

Inventor： Motofumi Saitoh ,  Hirohito Watanabe

IPC: H01L29/76

CPC classification number: H01L21/823842 ,  H01L21/28097 ,  H01L21/823835 ,  H01L21/823871 ,  H01L29/66545 ,  H01L29/6656 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes first and second active regions on a semiconductor substrate, separated by an element isolation region; a line-shaped electrode disposed from over the first to over the second active region via the element isolation region; first and second FETs including a gate insulating film on the first and second active regions, respectively, a gate electrode composed of the line-shaped electrode and a source/drain region. Parts of the line-shaped electrode over the first and second active regions are formed of different materials. The line-shaped electrode includes a diffusion restraining region having thickness in a direction perpendicular to the substrate thinner than that over the first and second active regions. The diffusion restraining region is over the element isolation region and spans the whole width of the line-shaped electrode in the gate length direction.

Abstract translation: 半导体器件包括半导体衬底上的第一和第二有源区，由元件隔离区隔开; 线状电极，其经由元件隔离区域从第一至第二有源区域上方设置; 第一和第二FET分别包括在第一和第二有源区上的栅极绝缘膜，由线状电极和源极/漏极区组成的栅电极。 第一和第二活性区域上的线状电极的部分由不同的材料形成。 线状电极包括扩散抑制区域，该扩散抑制区域在垂直于衬底的方向上的厚度小于第一和第二有源区域上的厚度。 扩散抑制区域在元件隔离区域的上方，并且跨越栅极长度方向的线状电极的整个宽度。

公开(公告)号：US20090096032A1

公开(公告)日：2009-04-16

申请号：US12093666

申请日：2006-10-18

Applicant: Motofumi Saitoh ,  Hirohito Watanabe

Inventor： Motofumi Saitoh ,  Hirohito Watanabe

IPC: H01L27/092 ,  H01L21/8234

CPC classification number: H01L21/823842 ,  H01L21/28097 ,  H01L21/823835 ,  H01L21/823871 ,  H01L29/66545 ,  H01L29/6656 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes first and second active regions on a semiconductor substrate, separated by an element isolation region; a line-shaped electrode disposed from over the first to over the second active region via the element isolation region; first and second FETs including a gate insulating film on the first and second active regions, respectively, a gate electrode composed of the line-shaped electrode and a source/drain region. Parts of the line-shaped electrode over the first and second active regions are formed of different materials. The line-shaped electrode includes a diffusion restraining region having thickness in a direction perpendicular to the substrate thinner than that over the first and second active regions. The diffusion restraining region is over the element isolation region and spans the whole width of the line-shaped electrode in the gate length direction.

Abstract translation: 半导体器件包括半导体衬底上的第一和第二有源区，由元件隔离区隔开; 线状电极，其经由元件隔离区域从第一至第二有源区域上方设置; 第一和第二FET分别包括在第一和第二有源区上的栅极绝缘膜，由线状电极和源极/漏极区组成的栅电极。 第一和第二活性区域上的线状电极的部分由不同的材料形成。 线状电极包括扩散抑制区域，该扩散抑制区域在垂直于衬底的方向上的厚度小于第一和第二有源区域上的厚度。 扩散抑制区域在元件隔离区域的上方，并且跨越栅极长度方向的线状电极的整个宽度。

公开(公告)号：US20050253181A1

公开(公告)日：2005-11-17

申请号：US11129440

申请日：2005-05-16

Applicant: Naohiko Kimizuka ,  Kiyotaka Imai ,  Yuri Masuoka ,  Toshiyuki Iwamoto ,  Motofumi Saitoh ,  Hirohito Watanabe ,  Masayuki Terai

Inventor： Naohiko Kimizuka ,  Kiyotaka Imai ,  Yuri Masuoka ,  Toshiyuki Iwamoto ,  Motofumi Saitoh ,  Hirohito Watanabe ,  Masayuki Terai

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/78 ,  H01L31/119

CPC classification number: H01L29/517 ,  H01L21/823857 ,  H01L29/4916 ,  H01L29/513 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The semiconductor device 100 comprises a silicon substrate 102, an N-type MOSFET 118 including a first high dielectric constant film 111 and a polycrystalline silicon film 114 formed on the silicon substrate 102, and a P-type MOSFET 120 including a second high dielectric constant film 112 and a polycrystalline silicon film 114 juxtaposed to N-type MOSFET 118 on the silicon substrate 102. The second high dielectric constant film 112 is formed to have the film thickness thinner than the film thickness of the first high dielectric constant film 111. The first high dielectric constant film 111 and the second high dielectric constant film 112 contains one or more element(s) selected from a group consisting of Hf and Zr.

Abstract translation: 半导体器件100包括硅衬底102，包括形成在硅衬底102上的第一高介电常数膜111和多晶硅膜114的N型MOSFET 118和包括第二高介电常数的P型MOSFET 120 膜112和与硅衬底102上的N型MOSFET 118并列的多晶硅膜114.第二高介电常数膜112形成为具有比第一高介电常数膜111的膜厚薄的膜厚度。 第一高介电常数膜111和第二高介电常数膜112包含从由Hf和Zr组成的组中选择的一种或多种元素。

公开(公告)号：US06853782B2

公开(公告)日：2005-02-08

申请号：US10194226

申请日：2002-07-15

Applicant: Kazunaga Kobayashi ,  Masahiro Kusakari ,  Matsuhiro Miyamoto ,  Hirohito Watanabe ,  Keiji Ohashi

Inventor： Kazunaga Kobayashi ,  Masahiro Kusakari ,  Matsuhiro Miyamoto ,  Hirohito Watanabe ,  Keiji Ohashi

IPC: G02B6/44

CPC classification number: G02B6/4429 ,  G02B6/4403

Abstract: An optical fiber drop cable includes an optical element portion having an optical fiber core wire and a pair of first tension members disposed parallel to the optical fiber core wire on both sides thereof in a sandwiching manner. The optical fiber core wire and the pair of first tension members are coated with a cable sheath. A long-scale cable support wire portion has a second tension member coated with a sheath. The optical element portion and the cable support wire portion are adhered parallel to each other. The first tension members are composed of a nonconductive material. A flexural rigidity of the optical element portion is in a range from 80 to 500 Nmm2.

Abstract translation: 光纤分路电缆包括具有光纤芯线的光学元件部分和以夹着方式平行于光纤芯线布置在其两侧的一对第一拉伸元件。 光纤芯线和一对第一张力构件涂覆有电缆护套。 长规格电缆支撑线部分具有涂覆有护套的第二张力构件。 光学元件部分和电缆支撑线部分彼此平行地粘合。 第一张力构件由非导电材料构成。 光学元件部的弯曲刚度在80〜500Nmm 2的范围内。

公开(公告)号：US06515322B1

公开(公告)日：2003-02-04

申请号：US08650948

申请日：1996-05-20

Applicant: Hirohito Watanabe

Inventor： Hirohito Watanabe

IPC: H01L2976

CPC classification number: H01L29/78391

Abstract: A nonvolatile semiconductor memory comprises a silicon substrate, a gate electrode formed through a gate insulator film on a principal surface of the semiconductor substrate, a pair of source/drain regions formed in a principal surface region of the semiconductor substrate to locate the gate electrode between the pair of source/drain regions. The gate insulator film is formed of a silicon oxide and/or silicon nitride film in contact with the principal surface of the semiconductor substrate, and a lead germanate film which is formed on the silicon oxide and/or silicon nitride film and which is a ferroelectric having a dielectric constant of not larger than 50.

Abstract translation: 非易失性半导体存储器包括硅衬底，通过半导体衬底的主表面上的栅绝缘膜形成的栅电极，形成在半导体衬底的主表面区域中的一对源/漏区，以将栅电极定位在 一对源极/漏极区域。 栅极绝缘膜由与半导体衬底的主表面接触的氧化硅和/或氮化硅膜形成，并且形成在氧化硅和/或氮化硅膜上并且是铁电体 介电常数不大于50。

公开(公告)号：US6033978A

公开(公告)日：2000-03-07

申请号：US754519

申请日：1996-11-21

Applicant: Kunihiro Fujii ,  Hirohito Watanabe

Inventor： Kunihiro Fujii ,  Hirohito Watanabe

IPC: H01L21/28 ,  H01L21/285 ,  H01L21/336 ,  H01L21/768 ,  H01L21/8238 ,  H01L21/4763 ,  H01L21/3205 ,  H01L21/44

CPC classification number: H01L21/28518 ,  H01L21/823814 ,  H01L21/823835 ,  H01L29/665

Abstract: Amorphous silicon layers are formed on an n-type single-crystal/poly-crystal layer and a p-type single-crystal/poly-crystal layer, and titanium is sputtered on the amorphous silicon layers; although the n-type dopant impurity are piled on the n-type single-crystal/poly-crystal layers, the amorphous silicon layers takes the piles of n-type dopant impurity thereinto, and promote the silicidation of the titanium layer.

Abstract translation: 在n型单晶/多晶层和p型单晶/多晶层上形成无定形硅层，并将钛溅射在非晶硅层上; 虽然n型掺杂剂杂质堆积在n型单晶/多晶层上，但是非晶硅层将n型掺杂剂杂质堆入其中，促进了钛层的硅化。