公开(公告)号：US20120292085A1

公开(公告)日：2012-11-22

申请号：US13455312

申请日：2012-04-25

Applicant: Hirohito Watanabe

Inventor： Hirohito Watanabe

IPC: H05K1/00 ,  H05K3/46

CPC classification number: H05K1/024 ,  H05K1/0219 ,  H05K1/0393 ,  H05K3/4635 ,  H05K2201/0141 ,  H05K2201/015

Abstract: Provided is a flexible printed circuit having a multilayered structure including three conductive layers. The flexible printed circuit includes: a first unit substrate formed of a first insulating layer made of liquid crystal polymer or fluorine resin and having a signal transmission circuit formed on one surface of the first insulating layer and a first conductive layer formed on the other surface thereof; a second unit substrate formed of a second insulating layer made of liquid crystal polymer or fluorine resin and having a second conductive layer formed on one surface of the second insulating layer; and an adhesive layer made of an epoxy thermal curing adhesive for bonding the first unit substrate and the second unit substrate in a state that the one surface of the first insulating layer is faced with the other surface of the second insulating layer.

Abstract translation: 提供一种具有包括三个导电层的多层结构的柔性印刷电路。 柔性印刷电路包括：第一单元基板，由由液晶聚合物或氟树脂制成的第一绝缘层形成，并且具有形成在第一绝缘层的一个表面上的信号传输电路和形成在其另一表面上的第一导电层 ; 第二单元基板，由由液晶聚合物或氟树脂制成的第二绝缘层形成，并且具有形成在所述第二绝缘层的一个表面上的第二导电层; 以及由环氧热固化型粘合剂制成的粘合剂层，用于在第一绝缘层的一个表面面对第二绝缘层的另一个表面的状态下接合第一单元基板和第二单元基板。

公开(公告)号：US20120279050A1

公开(公告)日：2012-11-08

申请号：US13462399

申请日：2012-05-02

Applicant: Hirohito WATANABE ,  Taiji OGAWA ,  Takaomi Tomonaga ,  Eriko TOMONAGA

Inventor： Hirohito WATANABE ,  Taiji OGAWA ,  Takaomi Tomonaga ,  Eriko TOMONAGA

IPC: H05K3/00

CPC classification number: H05K1/0269 ,  H05K3/06 ,  H05K2201/09781 ,  H05K2203/1545 ,  H05K2203/163

Abstract: Quickly making changes to etching conditions suppresses the production yield of printed wiring boards from being deteriorated. Disclosed is a method comprising: an etching step that comprises: preparing a conductor-clad base material continuous in a certain direction, the conductor-clad base material (1) having an insulating layer and one or more conductive layers formed on main surfaces of the insulating layer; and subjecting a predetermined region of a conductor layer of one main surface of the conductor-clad base material (1) to an etching process thereby to form a wiring pattern (1a) to be of a product and an inspection pattern (1b) to be used for inspection; a measuring step that measures a line width of the inspection pattern after the etching step; and a control step that controls an etching condition in the etching step based on the measured line width.

Abstract translation: 迅速改变蚀刻条件抑制了印刷电路板的生产成本的恶化。 公开了一种方法，包括：蚀刻步骤，包括：制备在一定方向上连续的导体包覆基材，所述导体包覆基材（1）具有绝缘层和形成在所述导体包覆基材的主表面上的一个或多个导电层 绝缘层; 并对导体包覆基材（1）的一个主表面的导体层的预定区域进行蚀刻处理，从而形成作为产品的布线图案（1a）和检查图案（1b） 用于检验; 测量步骤，其测量所述蚀刻步骤之后的所述检查图案的线宽; 以及控制步骤，其基于所测量的线宽来控制蚀刻步骤中的蚀刻条件。

公开(公告)号：US20100307797A1

公开(公告)日：2010-12-09

申请号：US12754929

申请日：2010-04-06

Applicant: Hirohito WATANABE

Inventor： Hirohito WATANABE

IPC: H05K1/02 ,  H05K1/09 ,  H05K3/00

CPC classification number: H05K3/281 ,  H05K1/0281 ,  H05K3/0058 ,  H05K3/386 ,  H05K2201/2009 ,  H05K2203/0195 ,  H05K2203/0278 ,  Y10T29/49124

Abstract: To improve reliability by preventing separation of a sheet material attached on a flexible printed circuit, provided is a flexible printed circuit including a printed board body and a reinforcing board. A leaked portion of an adhesive agent is formed to leak in an outward direction relative to an end surface of the reinforcing board. The leaked portion adheres to part of the end surface of the reinforcing board to be continuous from a lower end of the end surface to form an inclined surface tapered in the outward direction. The leaked portion is formed such that a portion thereof that covers the end surface has an adhesion height hA, as measured from an adhesive surface of the reinforcing board, of greater than 0% and not greater than 80% of the thickness H1 of the reinforcing board.

Abstract translation: 为了通过防止附着在柔性印刷电路上的片材的分离来提高可靠性，提供了包括印刷板主体和加强板的柔性印刷电路。 粘合剂的泄漏部形成为相对于加强板的端面在向外方向泄漏。 泄漏部分粘附在加强板的端面的一部分上，从端面的下端连续，形成向外方向倾斜的倾斜面。 泄漏部分形成为使得其覆盖端面的部分具有从加强板的粘合表面测量的粘合高度hA大于加强件的厚度H1的0％且不大于80％ 板。

公开(公告)号：US07679148B2

公开(公告)日：2010-03-16

申请号：US10521311

申请日：2003-07-16

Applicant: Heiji Watanabe ,  Hirohito Watanabe ,  Toru Tatsumi ,  Shinji Fujieda

Inventor： Heiji Watanabe ,  Hirohito Watanabe ,  Toru Tatsumi ,  Shinji Fujieda

IPC: H01L29/76

CPC classification number: H01L21/28202 ,  H01L21/28035 ,  H01L29/513 ,  H01L29/518 ,  H01L29/6656

Abstract: The task of the present invention is to enable formation of a gate insulating film structure having a good-quality interface between a silicon oxide film and silicon in an interface between a high dielectric constant thin film and a silicon substrate to provide a semiconductor device and a semiconductor manufacturing method which are capable of improving interface electrical characteristics, which has been a longstanding task in practical use of a high dielectric constant insulating film. A metal layer deposition process and a heat treatment process which supply metal elements constituting a high dielectric constant film on a surface of a base silicon oxide film 103 allow the metal elements to be diffused into the base silicon oxide film 103 to thereby form an insulating film structure 105 as a gate insulating film, after forming the base silicon oxide film 103 on a surface of a silicon substrate 101. The insulating film structure 105 including a silicate region comprises a silicon oxide film region, a silicate region, and a metal rich region, forming a silicate structure having composition modulation in which composition of metal increases as closer to an upper portion, and the composition of silicon increases as closer to a lower portion.

Abstract translation: 本发明的任务是能够在高介电常数薄膜和硅衬底之间的界面中形成具有氧化硅膜和硅之间良好界面的栅极绝缘膜结构，以提供半导体器件和 能够提高界面电特性的半导体制造方法，这在高介电常数绝缘膜的实际应用中是长期的任务。 在基底氧化硅膜103的表面上提供构成高介电常数膜的金属元素的金属层沉积工艺和热处理工艺允许金属元素扩散到基底氧化膜103中，从而形成绝缘膜 结构105作为栅极绝缘膜，在硅衬底101的表面上形成基底氧化膜103.包括硅酸盐区的绝缘膜结构105包括氧化硅膜区域，硅酸盐区域和富金属区域 形成具有组成调制的硅酸盐结构，其中金属的组成随着更靠近上部而增加，并且硅的组成随着更靠近下部而增加。

公开(公告)号：US20090250256A1

公开(公告)日：2009-10-08

申请号：US12302867

申请日：2007-05-23

Applicant: Yasuhiro Ouchi ,  Shinichi Nikaido ,  Haruo Miyazawa ,  Hirohito Watanabe ,  Katsuya Yamagami

Inventor： Yasuhiro Ouchi ,  Shinichi Nikaido ,  Haruo Miyazawa ,  Hirohito Watanabe ,  Katsuya Yamagami

IPC: H01R33/76 ,  H01R13/40 ,  H01R43/20 ,  H05K1/16

CPC classification number: H05K7/1069 ,  H01L2924/3511 ,  H01R12/52 ,  H01R12/714 ,  H01R13/2485 ,  Y10T29/53209

Abstract: A socket contact terminal for electrical connection between a connection portion formed of a metal conductor on a printed circuit board and a connection terminal of an IC package. The contact terminal comprises a metal terminal composed of a main columnar portion and arm portions on both sides and having an angular U shape and an elastomeric member attached to the metal terminal. A metal surface is exposed from the outer surface of each arm portion. The elastomeric member is firmly held between the arm portions of the metal terminal and exhibits a repulsive force when the arm portions are pressed in the direction that the arm portions approach each other.

Abstract translation: 一种插座接触端子，用于在由印刷电路板上的金属导体形成的连接部分和IC封装的连接端子之间进行电连接。 接触端子包括由主柱状部分和两侧的臂部分组成的并具有角度U形的金属端子和附接到金属端子的弹性体部件。 金属表面从每个臂部分的外表面露出。 弹性构件牢固地保持在金属端子的臂部之间，并且当臂部沿着臂部彼此接近的方向被按压时呈现排斥力。

公开(公告)号：US07072554B2

公开(公告)日：2006-07-04

申请号：US10614033

申请日：2003-07-08

Applicant: Hirohito Watanabe ,  Keiko Mitsuhashi ,  Tsuyoshi Shimomichi ,  Keiji Ohashi

Inventor： Hirohito Watanabe ,  Keiko Mitsuhashi ,  Tsuyoshi Shimomichi ,  Keiji Ohashi

IPC: G02B6/22

CPC classification number: G02B6/4482

Abstract: A distinctive optical fiber comprises an optical fiber core, distinctive layers, and a colored layer. A plurality of the distinctive layers including fine drops of ink having a specific particle size is disposed intermittently on the optical fiber core in the longitudinal direction of the optical fiber core. The colored layer is disposed on the distinctive layers and on the optical fiber core on which the distinctive layers are not disposed. The following five requirements are required for obtaining the distinctive optical fiber excellent in distinctiveness and with low transmission loss. The thickness of the colored layer is chosen so as to be larger than or equal to 2 μm and smaller than or equal to 10 μm. The thickness of the distinctive layers is chosen so as to be larger than or equal to 0.5 μm and smaller than or equal to 2.5 μm. The length of the distinctive layers is chosen so as to be larger than or equal to 1 mm and smaller than or equal to 15 mm. The interval of the distinctive layers is chosen so as to be in the range between 1 mm and 200 mm. The occupied ratio of the distinctive layers is chosen so as to be less than or equal to 20%. The major diameter of the fine drops of ink is chosen so as to be larger than or equal to 100 μm and smaller than or equal to 400 μm.

Abstract translation: 独特的光纤包括光纤芯，不同的层和着色层。 在光纤芯的长度方向上间隔地配置有包含具有特定粒径的细墨滴的多个特征层。 着色层设置在不同层上和未设置不同层的光纤芯上。 获得独特优异且传输损耗低的特殊光纤需要以下五个要求。 着色层的厚度选择为大于或等于2μm且小于等于10μm。 不同层的厚度选择为大于或等于0.5μm且小于或等于2.5μm。 不同层的长度选择为大于或等于1mm且小于或等于15mm。 选择不同层的间隔在1mm至200mm之间的范围内。 选择不同层的占有率小于或等于20％。 选择墨水的细滴的大直径为大于或等于100μm且小于或等于400μm。

公开(公告)号：US20050233526A1

公开(公告)日：2005-10-20

申请号：US10521311

申请日：2003-07-16

Applicant: Heiji Watanabe ,  Hirohito Watanabe ,  Toru Tatsumi ,  Shinji Fujieda

Inventor： Heiji Watanabe ,  Hirohito Watanabe ,  Toru Tatsumi ,  Shinji Fujieda

IPC: H01L21/28 ,  H01L29/51 ,  H01L21/336

CPC classification number: H01L21/28202 ,  H01L21/28035 ,  H01L29/513 ,  H01L29/518 ,  H01L29/6656

Abstract: The task of the present invention is to enable formation of a gate insulating film structure having a good-quality interface between a silicon oxide film and silicon in an interface between a high dielectric constant thin film and a silicon substrate to provide a semiconductor device and a semiconductor manufacturing method which are capable of improving interface electrical characteristics, which has been a longstanding task in practical use of a high dielectric constant insulating film. A metal layer deposition process and a heat treatment process which supply metal elements constituting a high dielectric constant film on a surface of a base silicon oxide film 103 allow the metal elements to be diffused into the base silicon oxide film 103 to thereby form an insulating film structure 105 as a gate insulating film, after forming the base silicon oxide film 103 on a surface of a silicon substrate 101. The insulating film structure 105 including a silicate region comprises a silicon oxide film region, a silicate region, and a metal rich region, forming a silicate structure having composition modulation in which composition of metal increases as closer to an upper portion, and the composition of silicon increases as closer to a lower portion.

Abstract translation: 本发明的任务是能够在高介电常数薄膜和硅衬底之间的界面中形成具有氧化硅膜和硅之间良好界面的栅极绝缘膜结构，以提供半导体器件和 能够提高界面电特性的半导体制造方法，这在高介电常数绝缘膜的实际应用中是长期的任务。 在基底氧化硅膜103的表面上提供构成高介电常数膜的金属元素的金属层沉积工艺和热处理工艺允许金属元素扩散到基底氧化膜103中，从而形成绝缘膜 结构105作为栅极绝缘膜，在硅衬底101的表面上形成基底氧化硅膜103之后。 包括硅酸盐区域的绝缘膜结构105包括氧化硅膜区域，硅酸盐区域和富金属区域，形成具有组成调节的硅酸盐结构，其中金属的组成随着上部的增加而增加， 硅越来越靠近下部。

公开(公告)号：US6024888A

公开(公告)日：2000-02-15

申请号：US748427

申请日：1996-11-13

Applicant: Hirohito Watanabe ,  Mitsusuke Kyogoku

Inventor： Hirohito Watanabe ,  Mitsusuke Kyogoku

IPC: H01L21/302 ,  H01L21/3065 ,  H01L21/311 ,  B44C1/22

CPC classification number: H01L21/31116

Abstract: In order to study an etching rate difference of a layer formed mainly with silicon dioxide on a wafer, a thermal oxide film (113) and layers of BSG (117), BPSG (125), and PSG (129) are laminated on a wafer and are etched in a gaseous etching atmosphere consisting essentially of hydrogen fluoride or a mixture of hydrogen fluoride and water vapor. The layers are etched with various etching rates which are higher than that of the thermal oxide film. The etching rate difference is a difference between the etching rate of each layer and an etching rate of the thermal oxide film. The layers may include impurities, such as boron and phosphorus, collectively as a part of a layer material of each layer. The etching rate difference depends on the layer material. Preferably, the gaseous etching atmosphere should have a reduced pressure. Alternatively, a water vapor partial pressure should not be greater than 2000 Pa. As a further alternative, either the layer or the gaseous etching atmosphere should be heated.

Abstract translation: 为了研究在晶片上主要由二氧化硅形成的层的蚀刻速率差，将热氧化膜（113）和BSG（117），BPSG（125）和PSG（129）的层叠在晶片上 并且在基本上由氟化氢或氟化氢和水蒸气的混合物组成的气体蚀刻气氛中进行蚀刻。 以比热氧化膜高的蚀刻速率蚀刻各层。 蚀刻速度差是各层的蚀刻速率与热氧化膜的蚀刻速度之差。 这些层可以包括诸如硼和磷的杂质，共同地作为每层的层材料的一部分。 蚀刻速率差取决于层材料。 优选地，气体蚀刻气氛应当具有减压。 或者，水蒸气分压不应大于2000Pa。作为另外的选择，应该加热层或气体蚀刻气氛。

公开(公告)号：US5372962A

公开(公告)日：1994-12-13

申请号：US11855

申请日：1993-02-01

Applicant: Toshiyuki Hirota ,  Ichirou Honma ,  Hirohito Watanabe ,  Masanobu Zenke

Inventor： Toshiyuki Hirota ,  Ichirou Honma ,  Hirohito Watanabe ,  Masanobu Zenke

IPC: H01L21/8242 ,  H01L27/108 ,  H01L21/70

CPC classification number: H01L27/10852 ,  H01L27/10808 ,  Y10S148/138 ,  Y10S438/964

Abstract: A capacitor incorporated in a semiconductor integrated circuit device is expected to have a large amount of capacitance without increase of the occupation area, and has a lower electrode increased in surface area by using a roughening technique selected from the group consisting of an anodizing technique, an anodic oxidation, a wet etching and a dry etching so that a surface of the lower electrode becomes porous, thereby increasing the capacitance.

Abstract translation: 期望并入半导体集成电路器件中的电容器具有大量的电容而不增加占用面积，并且通过使用选自以下的粗糙化技术，具有增加表面积的下电极，所述粗糙化技术包括阳极氧化技术， 阳极氧化，湿蚀刻和干蚀刻，使得下电极的表面变多孔，从而增加电容。

公开(公告)号：US5366917A

公开(公告)日：1994-11-22

申请号：US672073

申请日：1991-03-19

Applicant: Hirohito Watanabe ,  Toru Tatsumi

Inventor： Hirohito Watanabe ,  Toru Tatsumi

IPC: H01L21/02 ,  H01L27/108 ,  H01L29/92 ,  H01L21/205

CPC classification number: H01L27/10817 ,  H01L28/84 ,  H01L28/82 ,  H01L28/90 ,  Y10S438/964

Abstract: A method for fabricating a polycrystalline silicon having a roughed surface, which is useful for a capacitor electrode is disclosed. The method is featured by depositing a polycrystalline silicon layer in such a manner that grains of silicon are caused at the surface of the polycrystalline silicon layer. The polycrystalline silicon layer thus obtained has a large effective surface area and is suitable fur a capacitor electrode because of its increased effective surface area.

Abstract translation: 公开了一种用于制造具有粗糙表面的多晶硅的方法，其用于电容器电极。 该方法的特征在于以多晶硅层的表面上形成硅晶粒的方式沉积多晶硅层。 由此获得的多晶硅层由于其有效表面积增加而具有大的有效表面积并且适合于电容器电极。