公开(公告)号：US20110199808A1

公开(公告)日：2011-08-18

申请号：US13023738

申请日：2011-02-09

Applicant: Chul-woo YI ,  Seong-jin JANG ,  Jin-seok KWAK ,  Tai-young KO ,  Joung-yeal KIM ,  Sang-yun KIM ,  Sang-kyun PARK ,  Jung-bae LEE

Inventor： Chul-woo YI ,  Seong-jin JANG ,  Jin-seok KWAK ,  Tai-young KO ,  Joung-yeal KIM ,  Sang-yun KIM ,  Sang-kyun PARK ,  Jung-bae LEE

IPC: G11C5/06 ,  G11C5/10 ,  H01L21/02

CPC classification number: G11C5/063 ,  G11C7/062 ,  G11C7/065 ,  G11C7/18 ,  G11C11/4091 ,  G11C11/4097 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/10885 ,  H01L27/10897 ,  Y10T29/41

Abstract: A semiconductor memory device having an open bitline memory structure from which an edge dummy memory block is removed, the semiconductor memory device includes a memory block, an edge sense amplification block including a first sense amplifier having a first bitline, a first complementary bitline, and a first amplification circuit comprising a first transistor having a first size, a central sense amplification block including a second sense amplifier having a second bitline, a second complementary bitline, and a second amplification circuit comprising a second transistor having a second size different from the first size, a capacitor block electrically connected to the edge sense amplification block.

Abstract translation: 一种具有开放位线存储器结构的半导体存储器件，其中除去边缘伪存储器块，所述半导体存储器件包括存储器块，边沿读出放大块，其包括第一读出放大器，所述第一读出放大器具有第一位线，第一互补位线和 第一放大电路，包括具有第一尺寸的第一晶体管，中央读出放大块，包括具有第二位线的第二读出放大器，第二互补位线和第二放大电路，所述第二放大电路包括第二晶体管， 电容器块电连接到边缘检测放大块。

公开(公告)号：US20110141085A1

公开(公告)日：2011-06-16

申请号：US12771002

申请日：2010-04-30

Applicant: Yu Jin JANG ,  Jin Soo LEE ,  Jeong Mo YANG ,  Jeong In CHEON

Inventor： Yu Jin JANG ,  Jin Soo LEE ,  Jeong Mo YANG ,  Jeong In CHEON

IPC: G09G5/00

CPC classification number: H05B41/2858 ,  G09G3/3406 ,  G09G2330/026 ,  H05B41/382 ,  Y02B20/204

Abstract: Provided is an initial driving circuit of a backlight unit having a lamp unit provided with a plurality of lamps. In the initial driving circuit, an error amplifying unit 100 detects an error voltage VERO between a feedback voltage VFB corresponding to a current flowing to the lamp unit and a preset first reference voltage Vref11. A soft signal generation unit 200 generates a soft start signal VSS of the lamp unit. A high-frequency signal driving signal generating unit 300 generates a high-frequency driving signal VHF of the of the lamp unit. A high-frequency driving termination determining unit 400 generates a high-frequency driving termination signal SHE when the error voltage VERO is equal in voltage level to the soft start signal VSS. A high-frequency driving signal blocking unit 500 blocks the high-frequency driving signal VHF in advance when the high-frequency driving termination signal SHE is inputted.

Abstract translation: 提供了具有设置有多个灯的灯单元的背光单元的初始驱动电路。 在初始驱动电路中，误差放大单元100检测对应于流向灯单元的电流的反馈电压VFB与预设的第一参考电压Vref11之间的误差电压VERO。 软信号生成单元200生成灯单元的软启动信号VSS。 高频信号驱动信号生成单元300生成灯单元的高频驱动信号VHF。 高频驱动终止确定单元400当软电启动信号VSS的电压电平相等时，产生高频驱动终止信号SHE。 当输入高频驱动终止信号SHE时，高频驱动信号阻断单元500预先阻挡高频驱动信号VHF。

公开(公告)号：US20110135030A1

公开(公告)日：2011-06-09

申请号：US12929627

申请日：2011-02-04

Applicant: Seung-Jun Bae ,  Seong-Jin Jang ,  Beom-Sig Cho

Inventor： Seung-Jun Bae ,  Seong-Jin Jang ,  Beom-Sig Cho

IPC: H04L27/00

CPC classification number: G11C7/22 ,  H03K19/0966 ,  H04L7/0008 ,  H04L7/033 ,  H04L7/10

Abstract: A semiconductor device, a parallel interface system and methods thereof are provided. The example semiconductor device may include a reference clock transmitting block generating a reference clock signal, a plurality of first transceiver blocks, each of the plurality of first transceiver blocks transmitting at least one parallel data bit signal based on one of a plurality of phase-controlled transmitting sampling clock signals and a per-pin deskew block controlling a phase of a transmitting sampling clock signal to generate the phase-controlled sampling clock signals for the respective plurality of transceiver blocks, the per-pin deskew block controlling the phase of each phase-controlled transmitting sampling clock signal based on a phase skew between a given training data bit signal, among a plurality of training data bit signals, corresponding to a given first transceiver block and the reference clock signal in a first operation mode, and based on phase skew information relating to a phase skew between a given parallel data bit signal of the at least one parallel data bit signal and the reference clock signal in a second operation mode. An example method may include reducing skew based on a comparison between a plurality of transmitted training data bit signals and a corresponding plurality of received training data bit signals in a first mode of operation and reducing skew based on received phase skew information relating to a phase skew difference between a reference signal and a parallel data bit signal in a second mode of operation.

Abstract translation: 提供半导体器件，并行接口系统及其方法。 示例性半导体器件可以包括产生参考时钟信号的参考时钟发送块，多个第一收发器块，多个第一收发器块中的每一个基于多个相位控制的多个第一收发器块中的一个发送至少一个并行数据位信号 传输采样时钟信号和控制发射采样时钟信号的相位的每引脚偏移校正块，以产生相应的多个收发器模块的相位控制的采样时钟信号，每个引脚的去偏移块控制每个相位 - 基于相对于给定的第一收发器块的多个训练数据位信号中的给定训练数据位信号与第一操作模式中的参考时钟信号之间的相位偏移以及基于相位偏移的受控发送采样时钟信号 与至少一个并行数据的给定并行数据位信号之间的相位偏移有关的信息 在第二操作模式中的位信号和参考时钟信号。 示例性方法可以包括基于在第一操作模式中的多个发送的训练数据比特信号与对应的多个接收的训练数据比特信号之间的比较来减少偏斜，并且基于接收到的相位偏移相关的相位偏移信息减少偏斜 在第二操作模式中参考信号和并行数据位信号之间的差异。

公开(公告)号：US07953045B2

公开(公告)日：2011-05-31

申请号：US11225002

申请日：2005-09-14

Applicant: Youn-hee Han ,  Jung-ho Kim ,  Xiaoyu Liu ,  Jung-hoon Cheon ,  Hee-jin Jang

Inventor： Youn-hee Han ,  Jung-ho Kim ,  Xiaoyu Liu ,  Jung-hoon Cheon ,  Hee-jin Jang

IPC: H04W4/00 ,  H04W36/00

CPC classification number: H04L29/12311 ,  H04L29/12952 ,  H04L61/2084 ,  H04L61/6077 ,  H04W8/26 ,  H04W80/04

Abstract: A control method for a mobile terminal which connects to a router linked to an external network through at least one interface, including receiving a router advertisement message from the router through a first interface, determining whether prefix information of the received router advertisement message is identical with prefix information of a preset internet protocol (IP) configuration reuse group including the first interface, and generating an IP configuration of the first interface when the two prefix information are identical. Accordingly, at the time of a vertical handover, continuity of the A/V session can be maintained without having to use mobile IP technology.

Abstract translation: 一种用于通过至少一个接口连接到与外部网络链接的路由器的移动终端的控制方法，包括通过第一接口从路由器接收路由器通告消息，确定接收到的路由器通告消息的前缀信息是否与 包括第一接口的预设互联网协议（IP）配置重用组的前缀信息，以及当两个前缀信息相同时，生成第一接口的IP配置。 因此，在垂直切换时，可以维持A / V会话的连续性，而无需使用移动IP技术。

公开(公告)号：US07940014B2

公开(公告)日：2011-05-10

申请号：US12254520

申请日：2008-10-20

Applicant: Sang Cheol Shin ,  Byoung Own Min ,  Jung Chul Gong ,  Yu Jin Jang ,  Seung Kon Kong

Inventor： Sang Cheol Shin ,  Byoung Own Min ,  Jung Chul Gong ,  Yu Jin Jang ,  Seung Kon Kong

IPC: H05B37/02

CPC classification number: H05B33/0818

Abstract: Provided is an apparatus for driving a light emitting element. The apparatus includes a power unit, a light emitting element array, a constant-current circuit unit, and a voltage limiting circuit unit. The power unit supplies driving power. The light emitting element array includes a plurality of light emitting elements connected in series between an anode terminal connected to the power unit and a cathode terminal. The constant-current circuit unit maintains a constant current flowing through the light emitting element array according to a first tuning voltage. The voltage limiting circuit unit is connected between the cathode terminal of the light emitting element array and the constant-current circuit unit, and divides a total voltage applied between the cathode terminal of the light emitting element array and a ground according to a second tuning voltage to limit a voltage applied to the constant-current circuit unit below a predetermined voltage.

Abstract translation: 提供一种驱动发光元件的装置。 该装置包括功率单元，发光元件阵列，恒流电路单元和电压限制电路单元。 电源单元提供驱动电源。 发光元件阵列包括串联连接到电源单元的阳极端子和阴极端子之间的多个发光元件。 恒流电路单元根据第一调谐电压维持流过发光元件阵列的恒定电流。 电压限制电路单元连接在发光元件阵列的阴极端子和恒流电路单元之间，并且根据第二调谐电压将施加在发光元件阵列的阴极端子与地之间的总电压分压 以将施加到恒流电路单元的电压限制在预定电压以下。

公开(公告)号：US20110106127A1

公开(公告)日：2011-05-05

申请号：US13001844

申请日：2008-09-30

Applicant: Youn-Choul Shin ,  Suk-Jin Jang

Inventor： Youn-Choul Shin ,  Suk-Jin Jang

IPC: A61B17/34

CPC classification number: A61B5/1411 ,  A61B5/150022 ,  A61B5/150152 ,  A61B5/150167 ,  A61B5/150183 ,  A61B5/150259 ,  A61B5/150412 ,  A61B5/150519 ,  A61B5/150549 ,  A61B5/150618 ,  A61B5/150725 ,  A61B5/15113 ,  A61B5/15117 ,  A61B5/15123 ,  A61B5/1513 ,  A61B5/1519 ,  A61B5/15194

Abstract: The present invention concerns a blood withdrawal device comprising a one-piece cap and lancet and a painless impulse generator. The object of the present invention is to withdraw blood painlessly and to reduce a risk of a secondary infection. In order to achieve the object of the present invention, the blood withdrawal device of the present invention comprises a cap, a hollow body and a painless blood withdrawal device. The cap comprises a one-piece cap and lancet within which a lancet is movably combined and a hollow body for a detachable connection with a painless impulse generator or a main body of a blood withdrawal device. The hollow body comprises open ends on both side of the body thereby allowing the lancet to be detachable and the movable axis to be inserted within the body. The painless impulse generator is connected with the main body of the blood withdrawal device through a means for connecting with the main body of the blood withdrawal device defined at one side of the body thereby allowing the movement of the lancet needle and the cap by the movable axis. Therefore painless blood withdrawal is possible.

Abstract translation: 本发明涉及一种采血装置，包括一体式帽和刺血针以及无痛脉冲发生器。 本发明的目的是无痛地抽血并降低二次感染的风险。 为了实现本发明的目的，本发明的抽血装置包括帽，中空体和无痛抽血装置。 所述盖包括单件式的帽和柳叶刀，所述柳叶刀可移动地结合在一起，以及用于与无痛脉冲发生器或抽血装置的主体可拆卸连接的空心体。 中空体包括在主体两侧的开口端，从而允许刺血针可拆卸，并且可移动轴线插入体内。 无痛脉冲发生器通过与身体一侧限定的取血装置的主体连接的装置与抽血装置的主体连接，从而允许刺血针和帽由活动件 轴。 因此无痛抽血是可能的。

公开(公告)号：US07911862B2

公开(公告)日：2011-03-22

申请号：US12585428

申请日：2009-09-15

Applicant: Joung-Yeal Kim ,  Seong-Jin Jang ,  Kyoung-Ho Kim ,  Sam-Young Bang ,  Reum Oh

Inventor： Joung-Yeal Kim ,  Seong-Jin Jang ,  Kyoung-Ho Kim ,  Sam-Young Bang ,  Reum Oh

IPC: G11C7/00

CPC classification number: G11C8/10 ,  G11C7/1027 ,  G11C7/1045 ,  G11C7/1066 ,  G11C7/12 ,  G11C7/22 ,  G11C8/12 ,  G11C11/4076 ,  G11C11/4094

Abstract: A latency control circuit and method thereof and auto-precharge control circuit and method thereof are provided. The example latency control circuit may include a master unit activating at least one master signal based on a reference signal and an internal clock signal and a plurality of slave units receiving the at least one master signal, each of the plurality of slave units receiving a plurality of signals and outputting an output signal based at least in part upon one of the received plurality of signals. The example method of latency control may include receiving at least one master signal, the received at least one master signal activated based on a reference signal and an internal clock signal and receiving a plurality of signals and outputting an output signal based at least in part upon one of the received plurality of signals and latency information. The example auto-precharge control circuit may include a precharge command delay unit generating a plurality of first precharge command delay signals in response to an internal clock signal and a write auto-precharge command signal, at least one bank address delay unit outputting a delayed bank address signal and a precharge main signal generator outputting a precharge main signal to banks based on the delayed bank address signal. The method of performing a precharging operation with the auto-precharge control circuit may include delaying a bank address signal based on a minimum time interval between executed memory commands and outputting a precharge main signal to one or more memory banks based on the delayed bank address signal.

Abstract translation: 提供了一种延迟控制电路及其方法和自动预充电控制电路及其方法。 示例性延迟控制电路可以包括基于参考信号和内部时钟信号来激活至少一个主信号的主单元和接收至少一个主信号的多个从单元，多个从单元中的每一个接收多个 并且至少部分地基于所接收的多个信号之一输出输出信号。 等待时间控制的示例性方法可以包括：接收至少一个主信号，基于参考信号激活的所接收的至少一个主信号和内部时钟信号，并且接收多个信号并且至少部分地基于 所接收的多个信号和延迟信息中的一个。 示例性自动预充电控制电路可以包括预充电命令延迟单元，其响应于内部时钟信号和写自动预充电命令信号产生多个第一预充电命令延迟信号，至少一个存储体地址延迟单元输出延迟存储体 地址信号和预充电主信号发生器基于延迟的存储体地址信号向存储体输出预充电主信号。 利用自动预充电控制电路执行预充电操作的方法可以包括基于执行的存储器命令之间的最小时间间隔来延迟存储体地址信号，并且基于延迟的存储体地址信号向一个或多个存储器组输出预充电主信号 。

公开(公告)号：US07907693B2

公开(公告)日：2011-03-15

申请号：US11812438

申请日：2007-06-19

Applicant: Seung-Jun Bae ,  Seong-Jin Jang ,  Beom-Sig Cho

Inventor： Seung-Jun Bae ,  Seong-Jin Jang ,  Beom-Sig Cho

IPC: H04L7/00

CPC classification number: G11C7/22 ,  H03K19/0966 ,  H04L7/0008 ,  H04L7/033 ,  H04L7/10

Abstract: A semiconductor device, a parallel interface system and methods thereof are provided. The example semiconductor device may include a reference clock transmitting block generating a reference clock signal, a plurality of first transceiver blocks, each of the plurality of first transceiver blocks transmitting at least one parallel data bit signal based on one of a plurality of phase-controlled transmitting sampling clock signals and a per-pin deskew block controlling a phase of a transmitting sampling clock signal to generate the phase-controlled sampling clock signals for the respective plurality of transceiver blocks, the per-pin deskew block controlling the phase of each phase-controlled transmitting sampling clock signal based on a phase skew between a given training data bit signal, among a plurality of training data bit signals, corresponding to a given first transceiver block and the reference clock signal in a first operation mode, and based on phase skew information relating to a phase skew between a given parallel data bit signal of the at least one parallel data bit signal and the reference clock signal in a second operation mode. An example method may include reducing skew based on a comparison between a plurality of transmitted training data bit signals and a corresponding plurality of received training data bit signals in a first mode of operation and reducing skew based on received phase skew information relating to a phase skew difference between a reference signal and a parallel data bit signal in a second mode of operation.

公开(公告)号：US07868560B2

公开(公告)日：2011-01-11

申请号：US11808161

申请日：2007-06-07

Applicant: Jung Chul Gong ,  Byoung Own Min ,  Yu Jin Jang ,  Sang Cheol Shin

Inventor： Jung Chul Gong ,  Byoung Own Min ,  Yu Jin Jang ,  Sang Cheol Shin

IPC: H05B41/36

CPC classification number: H05B41/2828 ,  G09G3/3406 ,  Y02B20/186

Abstract: An inverter driving circuit for an LCD is switched on/off more stably to improve heating radiation characteristics and drive efficiency. In the driving circuit, a controller supplies a first driving signal. A level shifter provides a second driving signal. A first delay circuit delays a rising section of the first driving signal to provide the first driving signal. A second delay circuit delays a falling section of the second driving signal to provide the second driving signal. Also, a power switching circuit is provided. The inverter driving circuit for the LCD, when a switching device thereof is turned off, has less current flowing in the switching device, thereby generating less heat. In addition, the inverter driving circuit prevents heat generation caused by current flowing reversely in the switching device, thereby enhancing drive efficiency.

Abstract translation: 用于LCD的逆变器驱动电路更稳定地接通/断开以提高加热辐射特性和驱动效率。 在驱动电路中，控制器提供第一驱动信号。 电平移位器提供第二驱动信号。 第一延迟电路延迟第一驱动信号的上升部分以提供第一驱动信号。 第二延迟电路延迟第二驱动信号的下降部分以提供第二驱动信号。 另外，还提供了电源开关电路。 用于LCD的逆变器驱动电路当其开关装置关闭时，在开关装置中流动的电流较少，从而产生较少的热量。 此外，逆变器驱动电路防止在开关装置中逆流流动的热量产生，从而提高驱动效率。

公开(公告)号：US07826615B2

公开(公告)日：2010-11-02

申请号：US11049734

申请日：2005-02-04

Applicant: Su-hyun Nam ,  Myung-sun Kim ,  Yong-jin Jang ,  Sun-nam Lee ,  Jae-heung Lee ,  Sang-su Choi

Inventor： Su-hyun Nam ,  Myung-sun Kim ,  Yong-jin Jang ,  Sun-nam Lee ,  Jae-heung Lee ,  Sang-su Choi

IPC: H04N7/167

CPC classification number: H04N19/517 ,  H04N7/1675 ,  H04N19/61 ,  H04N21/2347

Abstract: A scrambling apparatus and method are provided for increasing randomness without damaging compression efficiency of total video data by selectively and randomly performing conversion when converting motion vector codes of compressed video data into other motion vector codes indicating other motion vector values, and more particularly, by performing conditional conversion only if a predetermined condition is satisfied when selective conversion of motion vector codes is performed. The scrambling apparatus includes a conversion motion vector code table generator generating a conversion motion vector code table comprising motion vector codes obtained by converting motion vector codes corresponding to motion vector values of input video data in a standard motion vector code table; and a conversion controller randomly determining whether a certain motion vector value is encoded using the conversion motion vector code table or the standard motion vector code table.

Abstract translation: 提供一种加扰装置和方法，用于通过在将压缩视频数据的运动矢量代码转换为指示其他运动矢量值的其他运动矢量代码时，通过有选择地和随机地执行转换来增加总体视频数据的压缩效率，而不损害总视频数据的压缩效率，更具体地说， 只有当执行运动矢量代码的选择性转换时满足预定条件时才进行条件转换。 该加扰装置包括：生成转换运动矢量代码表的转换运动矢量代码表，该转换运动矢量代码表包括通过对与运动矢量代码表中的输入图像数据的运动矢量值相对应的运动矢量代码而获得的运动矢量代码; 并且转换控制器随机地确定使用转换运动矢量代码表或标准运动矢量代码表是否对某个运动矢量值进行编码。