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    Trimming silicon fin width through oxidation and etch
    33.
    发明授权
    Trimming silicon fin width through oxidation and etch 有权
    通过氧化和蚀刻来修整硅片宽度

    公开(公告)号：US09412603B2

    公开(公告)日：2016-08-09

    申请号：US14548044

    申请日：2014-11-19

    Applicant: Applied Materials, Inc.

    Inventor： Ying Zhang ,  Hua Chung

    IPC: H01L29/78 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/02 ,  H01L21/311

    CPC classification number: H01L21/30604 ,  H01L21/02126 ,  H01L21/02236 ,  H01L21/02252 ,  H01L21/02255 ,  H01L21/02271 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/31116 ,  H01L21/31138 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/66818

    Abstract: Embodiments described herein generally relate to methods of forming sub-10 nm node FinFETs. Various processing steps are performed on a substrate to provide a trench defining a mandrel structure. Sidewalls of the mandrel structure and a bottom surface of the trench are oxidized and subsequently etched to reduce a width of the mandrel structure. The oxidation and etching of the mandrel structure may be repeated until a desired width of the mandrel structure is achieved. A semiconducting material is subsequently deposited on a regrowth region of the mandrel structure to form a fin structure. The oxidizing and etching the mandrel structure provides a method for forming the fin structure which can achieve sub-10 nm node dimensions and provide increasingly smaller FinFETs.

    Abstract translation: 本文描述的实施例通常涉及形成次10nm节点FinFET的方法。 在基板上执行各种处理步骤，以提供限定心轴结构的沟槽。 心轴结构的侧壁和沟槽的底表面被氧化并随后被蚀刻以减小心轴结构的宽度。 可以重复心轴结构的氧化和蚀刻，直到实现心轴结构的期望宽度。 随后将半导体材料沉积在心轴结构的再生长区域上以形成翅片结构。 氧化和蚀刻心轴结构提供了一种用于形成翅片结构的方法，其可实现10nm以下的节点尺寸并提供越来越小的FinFET。

    Methods for silicon recess structures in a substrate by utilizing a doping layer
    34.
    发明授权
    Methods for silicon recess structures in a substrate by utilizing a doping layer 有权
    通过利用掺杂层在衬底中的硅凹陷结构的方法

    公开(公告)号：US09214377B2

    公开(公告)日：2015-12-15

    申请号：US14068312

    申请日：2013-10-31

    Applicant: APPLIED MATERIALS, INC.

    Inventor： Ying Zhang ,  Hua Chung ,  Srinivas D. Nemani ,  Ludovic Godet

    IPC: H01L21/76 ,  H01L21/762 ,  H01L21/265

    CPC classification number: H01L21/76224 ,  H01L21/2236 ,  H01L21/26513 ,  H01L21/6831 ,  H01L29/66795

    Abstract: Embodiments of the present invention provide a methods for forming silicon recess structures in a substrate with good process control, particularly suitable for manufacturing three dimensional (3D) stacking of fin field effect transistor (FinFET) for semiconductor chips. In one embodiment, a method of forming recess structures in a substrate includes etching a first portion of a substrate defined by a second portion formed in the substrate until a doping layer formed in the substrate is exposed.

    Abstract translation: 本发明的实施例提供了一种用于在具有良好的工艺控制的衬底中形成硅凹陷结构的方法，特别适用于制造用于半导体芯片的鳍式场效应晶体管（FinFET）的三维（3D）堆叠。 在一个实施例中，在衬底中形成凹陷结构的方法包括蚀刻由形成在衬底中的第二部分限定的衬底的第一部分，直到形成在衬底中的掺杂层露出。

    Trench formation with CD less than 10 NM for replacement Fin growth
    36.
    发明授权
    Trench formation with CD less than 10 NM for replacement Fin growth 有权
    CD的海沟形成小于10海里，以替代鳍生长

    公开(公告)号：US08993419B1

    公开(公告)日：2015-03-31

    申请号：US14045467

    申请日：2013-10-03

    Applicant: Applied Materials, Inc.

    Inventor： Ying Zhang ,  Hua Chung

    IPC: H01L21/302 ,  H01L29/66

    CPC classification number: H01L29/1037 ,  H01L21/02538 ,  H01L21/265 ,  H01L21/31055 ,  H01L21/31111 ,  H01L21/31144 ,  H01L29/66795 ,  H01L29/7848

    Abstract: Embodiments described herein generally relate to methods of forming sub-10 nm node FinFETs. Various processing steps may be performed on a substrate to provide a trench over which a dielectric layer is conformally deposited. The dielectric layer is subsequently etched within the trench to expose the underlying substrate and a semiconductive material is deposited in the trench to form a fin structure. The processes of forming the trench, depositing the dielectric layer, and forming the fin structure can achieve sub-10 nm node dimensions and provide increasingly smaller FinFETs.

    Abstract translation: 本文描述的实施例通常涉及形成次10nm节点FinFET的方法。 可以在衬底上执行各种处理步骤，以提供在其上共形沉积介电层的沟槽。 随后在沟槽内蚀刻电介质层以暴露下面的衬底，并且半导体材料沉积在沟槽中以形成鳍结构。 形成沟槽，沉积介电层和形成鳍结构的工艺可以实现10nm以下的节点尺寸并提供越来越小的FinFET。

    AEROSOL DEPOSITION COATING FOR SEMICONDUCTOR CHAMBER COMPONENTS
    37.
    发明申请
    AEROSOL DEPOSITION COATING FOR SEMICONDUCTOR CHAMBER COMPONENTS 有权
    用于半导体室组件的气溶胶沉积涂料

    公开(公告)号：US20140349073A1

    公开(公告)日：2014-11-27

    申请号：US14282824

    申请日：2014-05-20

    Applicant: Applied Materials, Inc.

    Inventor： Jennifer Y. Sun ,  Biraja Kanungo ,  Tom Cho ,  Ying Zhang

    IPC: H01J37/32

    CPC classification number: H01J37/32807 ,  C23C24/04 ,  H01J37/3244 ,  Y10T428/24413

    Abstract: A method for coating a component for use in a semiconductor chamber for plasma etching includes providing the component and loading the component in a deposition chamber. A pressure in the deposition chamber is reduced to below atmospheric pressure. A coating is deposited on the component by spraying an aerosol comprising a suspension of a first type of metal oxide nanoparticle and a second type of metal oxide nanoparticle onto the component at approximately room temperature.

    Abstract translation: 用于涂覆用于等离子体蚀刻的半导体室中的部件的方法包括提供部件并将部件装载到沉积室中。 沉积室中的压力降低到低于大气压。 通过在大约室温下将包含第一类金属氧化物纳米颗粒和第二类型的金属氧化物纳米颗粒的悬浮液的气溶胶喷涂到组分上来将组分沉积在组分上。

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