公开(公告)号：US10152425B2

公开(公告)日：2018-12-11

申请号：US15180807

申请日：2016-06-13

Applicant: Advanced Micro Devices, Inc.

Inventor： Paul James Moyer

IPC: G06F12/0891 ,  G06F12/0897 ,  G06F12/128

Abstract: A processing system selects entries for eviction at one cache based at least in part on the validity status of corresponding entries at a different cache. The processing system includes a memory hierarchy having at least two caches, a higher level cache and a lower level cache. The lower level cache monitors which locations of the higher level cache have been indicated as invalid and, when selecting an entry of the lower level cache for eviction to the higher level cache, selects the entry based at least in part on whether the selected cache entry will be stored at an invalid cache line of the higher level cache.

公开(公告)号：US20180024931A1

公开(公告)日：2018-01-25

申请号：US15215033

申请日：2016-07-20

Applicant: Advanced Micro Devices, Inc.

Inventor： Paul James Moyer

IPC: G06F12/0862

CPC classification number: G06F12/0862 ,  G06F2212/6026

Abstract: A processor applies a transfer policy to a portion of a cache based on access metrics for different test regions of the cache, wherein each test region applies a different transfer policy for data in cache entries that were stored in response to a prefetch requests but were not the subject of demand requests. One test region applies a transfer policy under which unused prefetches are transferred to a higher level cache in a cache hierarchy upon eviction from the test region of the cache. The other test region applies a transfer policy under which unused prefetches are replaced without being transferred to a higher level cache (or are transferred to the higher level cache but stored as invalid data) upon eviction from the test region of the cache.

公开(公告)号：US20180018264A1

公开(公告)日：2018-01-18

申请号：US15211547

申请日：2016-07-15

Applicant: Advanced Micro Devices, Inc.

Inventor： Paul James Moyer

IPC: G06F12/0844 ,  G06F12/0868

Abstract: A processing system indicates the pendency of a memory access request for data at the cache entry that is assigned to store the data in response to the memory access request. While executing instructions, the processor issues requests for data to the cache most proximal to the processor. In response to a cache miss, the cache controller identifies an entry of the cache to store the data in response to the memory access request, and stores an indication that the memory access request is pending at the identified cache entry. If the cache controller receives a subsequent memory access request for the data while the memory access request is pending at the higher level of the memory hierarchy, the cache controller identifies that the memory access request is pending based on the indicator stored at the entry.