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    STACKED MICROELECTRONIC ASSEMBLY HAVING INTERPOSER CONNECTING ACTIVE CHIPS
    31.
    发明申请
    STACKED MICROELECTRONIC ASSEMBLY HAVING INTERPOSER CONNECTING ACTIVE CHIPS 有权
    具有连接主动插座的插座的堆叠式微电子组件

    公开(公告)号：US20120139094A1

    公开(公告)日：2012-06-07

    申请号：US12958866

    申请日：2010-12-02

    Applicant: Belgacem Haba ,  Vage Oganesian ,  Ilyas Mohammed ,  Piyush Savalia ,  Craig Mitchell

    Inventor： Belgacem Haba ,  Vage Oganesian ,  Ilyas Mohammed ,  Piyush Savalia ,  Craig Mitchell

    IPC: H01L29/41 ,  H01L21/44

    CPC classification number: H01L25/0657 ,  H01L21/486 ,  H01L21/76898 ,  H01L23/36 ,  H01L23/481 ,  H01L23/49822 ,  H01L23/49827 ,  H01L25/16 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2924/15311

    Abstract: A microelectronic assembly can include first and second microelectronic elements each embodying active semiconductor devices adjacent a front surface thereof, and having an electrically conductive pad exposed at the respective front surface. An interposer of material having a CTE less than 10 ppm/° C. has first and second surfaces attached to the front surfaces of the respective first and second microelectronic elements, the interposer having a second conductive element extending within an opening in the interposer. First and second conductive elements extend within openings extending from the rear surface of a respective microelectronic element of the first and second microelectronic elements towards the front surface of the respective microelectronic element. In one example, one or more of the first or second conductive elements extends through the respective first or second pad, and the conductive elements contact the exposed portions of the second conductive element to provide electrical connection therewith.

    Abstract translation: 微电子组件可以包括第一和第二微电子元件，每个微电子元件各自体现邻近其前表面的有源半导体器件，并且具有在相应的前表面处暴露的导电焊盘。 具有小于10ppm /℃的CTE的材料的插入件具有附接到相应的第一和第二微电子元件的前表面的第一和第二表面，所述插入件具有在插入器的开口内延伸的第二导电元件。 第一和第二导电元件在从第一和第二微电子元件的相应微电子元件的后表面朝向相应微电子元件的前表面延伸的开口内延伸。 在一个示例中，第一或第二导电元件中的一个或多个延伸穿过相应的第一或第二焊盘，并且导电元件接触第二导电元件的暴露部分以提供与其的电连接。

    NON-LITHOGRAPHIC FORMATION OF THREE-DIMENSIONAL CONDUCTIVE ELEMENTS
    32.
    发明申请
    NON-LITHOGRAPHIC FORMATION OF THREE-DIMENSIONAL CONDUCTIVE ELEMENTS 有权
    非线性形成三维导电元件

    公开(公告)号：US20120018894A1

    公开(公告)日：2012-01-26

    申请号：US12842669

    申请日：2010-07-23

    Applicant: Vage Oganesian ,  Belgacem Haba ,  Ilyas Mohammed ,  Craig Mitchell ,  Piyush Savalia

    Inventor： Vage Oganesian ,  Belgacem Haba ,  Ilyas Mohammed ,  Craig Mitchell ,  Piyush Savalia

    IPC: H01L23/498 ,  H01L21/768

    CPC classification number: H01L21/76879 ,  H01L21/76802 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/4985 ,  H01L23/5226 ,  H01L24/06 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/00

    Abstract: A method of forming a conductive element on a substrate and the resulting assembly are provided. The method includes forming a groove in a sacrificial layer overlying a dielectric region disposed on a substrate. The groove preferably extends along a sloped surface of the substrate. The sacrificial layer is preferably removed by a non-photolithographic method, such as ablating with a laser, mechanical milling, or sandblasting. A conductive element is formed in the groove. The grooves may be formed. The grooves and conductive elements may be formed along any surface of the substrate, including within trenches and vias formed therein, and may connect to conductive pads on the front and/or rear surface of the substrate. The conductive elements are preferably formed by plating and may or may not conform to the surface of the substrate.

    Abstract translation: 提供了在基板上形成导电元件的方法和所得到的组件。 该方法包括在覆盖设置在基板上的电介质区域上的牺牲层中形成凹槽。 槽优选地沿着衬底的倾斜表面延伸。 牺牲层优选通过非光刻方法去除，例如用激光烧蚀，机械研磨或喷砂。 在沟槽中形成导电元件。 可以形成凹槽。 凹槽和导电元件可以沿着衬底的任何表面形成，包括在其中形成的沟槽和通孔内，并且可以连接到衬底的前表面和/或后表面上的导电焊盘。 导电元件优选通过电镀形成，并且可以或可以不与基板的表面一致。

    Microelectronic assemblies having very fine pitch stacking
    35.
    发明申请
    Microelectronic assemblies having very fine pitch stacking 有权
    微电子组件具有非常细的间距堆积

    公开(公告)号：US20070148819A1

    公开(公告)日：2007-06-28

    申请号：US11318164

    申请日：2005-12-23

    Applicant: Belgacem Haba ,  Craig Mitchell

    Inventor： Belgacem Haba ,  Craig Mitchell

    IPC: H01L21/00 ,  H01L21/44

    CPC classification number: H01L25/50 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/16 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15331 ,  H01L2924/3011 ,  H01L2924/3511

    Abstract: A microelectronic assembly includes two or more microelectronic packages stacked at a fine pitch, which is finer than the pitch that is possible when using solder balls for making the joint. Each stackable package desirably includes a substrate having pins projecting from one surface of the substrate and solder balls projecting from the other surface of the substrate. Each stackable package may have one or more die attached to one or more of the surfaces of the substrate. In certain embodiments, die may be attached to both surfaces of the substrate. The dies may be electrically interconnected with the substrate using wire bonds, flip chip bonding, leads and/or stud bumping. The die may be encapsulated in an encapsulated material, under-filled or glob topped. In certain preferred embodiments, the combination of the conductive post height and ball height is equal to or greater than the height of the encapsulated or molded chip structure. The combination of the conductive post height and the ball height must be at least equal to the height of the encapsulated chip structure so that the conductive elements are able to span the gap between layers of the assembly. After the tips of the conductive pads are in contact with the solder masses, the solder masses are reflowed to form a permanent electrical interconnection between the stacked microelectronic packages. During reflow, the reflowed solder will wick up around the conductive posts to form elongated solder columns. In addition, when the solder is reflowed, surface tension pulls the opposing layers of the assembly toward one another and provides a self-centering action for the conductive posts.

    Abstract translation: 微电子组件包括以细间距堆叠的两个或更多个微电子封装，其比使用用于制造接头的焊球可能的间距更细。 每个可堆叠封装理想地包括具有从基板的一个表面突出的销和从该基板的另一个表面突出的焊球的基板。 每个可堆叠的封装可以具有一个或多个管芯附接到衬底的一个或多个表面。 在某些实施例中，管芯可以附接到衬底的两个表面。 模具可以使用引线接合，倒装芯片接合，引线和/或螺柱凸起与基板电互连。 芯片可以封装在封装的材料中，未充满的或者顶部的。 在某些优选实施例中，导电柱高度和球高度的组合等于或大于封装或模制芯片结构的高度。 导电柱高度和球高度的组合必须至少等于封装的芯片结构的高度，使得导电元件能够跨越组件的层之间的间隙。 在导电焊盘的尖端与焊料块接触之后，焊料质量被回流以在堆叠的微电子封装之间形成永久的电互连。 在回流期间，回流的焊料将在导电柱周围吸收，形成细长的焊料柱。 此外，当焊料回流时，表面张力将组件的相对的层相互拉向彼此，并为导电柱提供自对中动作。

    Semiconductor chip assembly
    40.
    发明授权
    Semiconductor chip assembly 有权
    半导体芯片组装

    公开(公告)号：US06169328A

    公开(公告)日：2001-01-02

    申请号：US09246056

    申请日：1999-02-08

    Applicant: Craig Mitchell ,  Mike Warner ,  Jim Behlen

    Inventor： Craig Mitchell ,  Mike Warner ,  Jim Behlen

    IPC: H01L2348

    CPC classification number: H01L21/56 ,  H01L21/563 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/4985 ,  H01L24/72 ,  H01L24/75 ,  H01L24/81 ,  H01L2224/16 ,  H01L2224/73203 ,  H01L2224/75 ,  H01L2224/81801 ,  H01L2224/83136 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/16152 ,  H01L2924/19041 ,  H01L2924/19043 ,  H05K1/118 ,  H05K3/361 ,  H05K3/4084 ,  H05K2201/0133 ,  H05K2201/0394 ,  H05K2201/0397 ,  H05K2201/09081 ,  H05K2201/091 ,  H05K2203/063 ,  H01L2924/00

    Abstract: A semiconductor chip package structure for providing a reliable interface between a semiconductor chip and a PWB to accommodate for the thermal coefficient of expansion mismatch therebetween. The interface between a chip and a PWB is comprised of a package substrate having a plurality of compliant pads defining channels therebetween. The package substrate is typically comprised of a flexible dielectric sheet that has leads and terminals on at least one surface thereof. The pads have a first coefficient of thermal expansion (“CTE”) and are comprised of a material having a fairly low modulus of elasticity. An encapsulant having a second CTE lower than the CTE of the compliant pads is disposed within the channels to form a uniform encapsulation layer. The pads are in rough alignment with the conductive terminals on the package substrate thereby allowing independent movement of the terminals during thermal cycling of the chip. The encapsulant encases the conductive leads electrically connecting the terminals to chip contacts on a face surface of the chip. The lower CTE of the encapsulant controls the flexing of the conductive leads so that the leads do not prematurely fatigue and become unreliable while the lower modulus compliant pads relieve the stress on the solder balls induced by the CTE mismatch of the chip and the PWB.

    Abstract translation: 一种用于在半导体芯片和PWB之间提供可靠接口的半导体芯片封装结构，以适应其间的热膨胀系数不匹配。 芯片和PWB之间的接口包括具有多个在其间形成通道的柔性衬垫的封装衬底。 封装基板通常由在其至少一个表面上具有引线和端子的柔性电介质片构成。 垫具有第一热膨胀系数（“CTE”），并且由具有相当低的弹性模量的材料组成。 具有比柔性焊盘的CTE低的第二CTE的密封剂设置在通道内以形成均匀的封装层。 焊盘与封装衬底上的导电端子粗略对准，从而允许在芯片的热循环期间端子的独立移动。 密封剂封装导电引线，将引线电连接到芯片的表面上的芯片触点。 密封剂的较低CTE控制导电引线的弯曲，使得引线不会过早地疲劳并变得不可靠，而较低模量的柔性焊盘缓解由芯片和PWB的CTE不匹配引起的焊球上的应力。

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