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公开(公告)号：US11822427B2
公开(公告)日：2023-11-21
申请号：US17823131
申请日：2022-08-30
Applicant: Graphcore Limited
Inventor： Stephen Felix , Daniel Wilkinson , Graham Bernard Cunningham
CPC classification number: G06F11/1068 , G06F11/0772 , G06F11/1004 , H03K19/21
Abstract: Signature generation circuitry is configured to update a signature in response to each of a plurality of writes to memory. The signature is updated by performing bitwise operations between current bit values of the signature and at least some of the bits written to memory in response a write. The bitwise operation are order-independent such that the resulting signature is the same irrespective of the order in which the writes are used to update the signature. The signatures are formed in an order-independent manner such that, if no errors have occurred in generating the data to be written to be memory, the signatures will match. In this way, a compact signature is developed that is suitable export from the data processing device for checking against a corresponding data processing device of a machine running a duplicate application.
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公开(公告)号：US11680965B2
公开(公告)日：2023-06-20
申请号：US17814247
申请日：2022-07-22
Applicant: Graphcore Limited
Inventor： Stephen Felix , Daniel John Pelham Wilkinson
IPC: G06F1/06 , G01R19/165 , H03K5/14 , G01R17/02
CPC classification number: G01R19/16504 , G01R17/02 , G01R19/16552 , G06F1/06 , H03K5/14
Abstract: During normal operation of a processor, voltage droop is likely to occur and there is, therefore, a need for techniques for rapidly and accurately detecting this droop so as to reduce the probability of circuit timing failures. The droop detector described herein uses a tap sampled delay line in which a clock signal is split along two separate paths. Each of the taps in the paths are separated by two inverter delays such that the set of samples produced represent sample values of the clock signal that are each separated by a single inverter delay without inversion of the first clock signal between the samples.
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公开(公告)号：US11461175B1
公开(公告)日：2022-10-04
申请号：US17447954
申请日：2021-09-17
Applicant: Graphcore Limited
Inventor： Stephen Felix , Daniel Wilkinson , Graham Bernard Cunningham
Abstract: Signature generation circuitry is configured to update a signature in response to each of a plurality of writes to memory. The signature is updated by performing bitwise operations between current bit values of the signature and at least some of the bits written to memory in response a write. The bitwise operation are order-independent such that the resulting signature is the same irrespective of the order in which the writes are used to update the signature. The signatures are formed in an order-independent manner such that, if no errors have occurred in generating the data to be written to be memory, the signatures will match. In this way, a compact signature is developed that is suitable export from the data processing device for checking against a corresponding data processing device of a machine running a duplicate application.
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公开(公告)号：US11442082B2
公开(公告)日：2022-09-13
申请号：US17082667
申请日：2020-10-28
Applicant: Graphcore Limited
Inventor： Stephen Felix , Daniel John Pelham Wilkinson
IPC: G06F1/06 , G01R19/165 , H03K5/14 , G01R17/02
Abstract: During normal operation of a processor, voltage droop is likely to occur and there is, therefore, a need for techniques for rapidly and accurately detecting this droop so as to reduce the probability of circuit timing failures. The droop detector described herein uses a tap sampled delay line in which a clock signal is split along two separate paths. Each of the taps in the paths are separated by two inverter delays such that the set of samples produced represent sample values of the clock signal that are each separated by a single inverter delay without inversion of the first clock signal between the samples.
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公开(公告)号：US20220253279A1
公开(公告)日：2022-08-11
申请号：US17660688
申请日：2022-04-26
Applicant: Graphcore Limited
Inventor： Jonathan Mangnall , Stephen Felix
Abstract: An execution unit for a processor, the execution unit comprising: a look up table having a plurality of entries, each of the plurality of entries comprising an initial estimate for a result of an operation; a preparatory circuit configured to search the look up table using an index value dependent upon the operand to locate an entry comprising a first initial estimate for a result of the operation; a plurality of processing circuits comprising at least one multiplier circuit; and control circuitry configured to provide the first initial estimate to the at least one multiplier circuit of the plurality of processing circuits so as perform processing, by the plurality of processing units, of the first initial estimate to generate the function result, said processing comprising applying one or more Newton Raphson iterations to the first initial estimate.
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Patent Agency Ranking
公开(公告)号：US11328015B2
公开(公告)日：2022-05-10
申请号：US16395345
申请日：2019-04-26
Applicant: Graphcore Limited
Inventor： Jonathan Mangnall , Stephen Felix
IPC: G06F17/17 , G06F16/901 , G06F1/03
Abstract: A function approximation system is disclosed for determining output floating point values of functions calculated using floating point numbers. Complex functions have different shapes in different subsets of their input domain, making them difficult to predict for different values of the input variable. The function approximation system comprises an execution unit configured to determine corresponding values of a given function given a floating point input to the function; a plurality of look up tables for each function type; a correction table of values which determines if corrections to the output value are required; and a table selector for finding an appropriate table for a given function.
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公开(公告)号：US11176066B2
公开(公告)日：2021-11-16
申请号：US16395846
申请日：2019-04-26
Applicant: Graphcore Limited
Inventor： Richard Luke Southwell Osborne , Stephen Felix
Abstract: The present disclosure relates to a method of scheduling messages to be exchanged between tiles in a computer where there is a fixed transmission time between sending and receiving tiles. According to the method a total size of message data to be sent or received by each tile is determined. One of the tiles is selected based at least on the size of the message data to schedule a first message. The first message to be scheduled is selected from the set of messages on that tile. In order to schedule the message the other end points of this selected message are determined, and then respective time slots are allocated at the sending and receiving tiles for that message. The size of the selected message is then deducted from each of the tiles acting as end points for the message, and then the sequence is carried out again until all messages have been scheduled. This technique optimises message exchange in an exchange phase of a BSP system.
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公开(公告)号：US11169777B2
公开(公告)日：2021-11-09
申请号：US16395328
申请日：2019-04-26
Applicant: Graphcore Limited
Inventor： Alan Graham Alexander , Edward Andrews , Stephen Felix , Mrudula Chidambar Gore
Abstract: A method and apparatus for handling overflow conditions resulting from arithmetic operations involving floating point numbers. An indication is stored as part of a thread's context indicating one of two possible modes for handling overflow conditions. In a first mode, a result of an arithmetic operation is set to the limit representable in the floating point format. In a second mode, a result of an arithmetic operation is set to a NaN.
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公开(公告)号：US10820409B1
公开(公告)日：2020-10-27
申请号：US16804955
申请日：2020-02-28
Applicant: Graphcore Limited
Inventor： Stephen Felix
Abstract: According to a first aspect, there is provided a computer structure comprising a first silicon substrate and a second silicon substrate. Computer circuitry configured to perform computing operations is formed in the first silicon substrate, which has a self-supporting depth and an inner facing surface. A plurality of distributed capacitance units are formed in the second silicon substrate, which has an inner facing surface located in overlap with the inner facing surface of the first substrate and is connected to the first substrate via a set of connectors arranged extending depthwise of the structure between the inner facing surfaces. The inner facing surfaces have matching planar surface dimensions. The second substrate has an outer facing surface on which are arranged a plurality of connector terminals for connecting the computer structure to a supply voltage. The second substrate has a smaller depth than the first substrate.
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公开(公告)号：US10817444B2
公开(公告)日：2020-10-27
申请号：US16525833
申请日：2019-07-30
Applicant: Graphcore Limited
Inventor： Daniel John Pelham Wilkinson , Richard Luke Southwell Osborne , Stephen Felix , Graham Bernard Cunningham , Alan Graham Alexander
Abstract: A system comprising an arrangement of multiple processor modules, and an external interconnect for communicating data in the form of packets to outside the arrangement. The interconnect comprises an exchange block configured to provide flow control. One of the processor modules is arranged to send an exchange request message to the exchange block on behalf of others with data to send outside the arrangement. The exchange block sends an exchange-on message to a first of these processor modules, to cause the first module to start sending packets via the interconnect. Then, once this processor module has sent its last data packet, the exchange block sends an exchange-off message to this processor module to cause it to stop sending packets, and sends another exchange-on message to the next processor module with data to send, and so forth.
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