公开(公告)号：US12124699B2

公开(公告)日：2024-10-22

申请号：US18053948

申请日：2022-11-09

Applicant: Graphcore Limited

Inventor： Alan Alexander ,  Edward Andrews ,  Peter Hedinger

IPC: G06F3/06 ,  G06F9/30

CPC classification number: G06F3/0608 ,  G06F3/0659 ,  G06F3/067 ,  G06F9/30036 ,  G06F9/30109

Abstract: A new type of instruction and a control register for the new type of instruction are provided to handle data that may be misaligned in memory. A first part of data (which may be misaligned in memory) is loaded into a first set of registers by loading a first atom containing the first part of data into registers. The pack instruction is executed by an execution unit to place part of data (whose length and starting position are indicated by second and third values in a control register) from one set of registers into an identified location (identified by a first value in the control register) in another set of registers.

公开(公告)号：US20230084298A1

公开(公告)日：2023-03-16

申请号：US17653012

申请日：2022-03-01

Applicant: Graphcore Limited

Inventor： Sam Chesney ,  Alan Graham Alexander ,  Richard Luke Southwell Osborne ,  Edward Andrews

IPC: G06F12/0804 ,  G06F9/30

Abstract: For certain applications, parts of the application data held in memory of a processing device (e.g. that are produced as a result of operations performed by the execution unit) are arranged in regular repeating patterns in the memory, and therefore, the execution unit may set up a suitable striding pattern for use by a send engine. The send engine accesses the memory at locations in accordance with the configured striding pattern so as to access a plurality of items of data that are arranged together in a regular pattern. In a similar manner as done for sends, the execution may set up a striding pattern for use by a receive engine. The receive engine, upon receiving a plurality of items of data, causes those items of data to be stored at locations in the memory, as determined in accordance with the configured striding pattern.

公开(公告)号：US11169777B2

公开(公告)日：2021-11-09

申请号：US16395328

申请日：2019-04-26

Applicant: Graphcore Limited

Inventor： Alan Graham Alexander ,  Edward Andrews ,  Stephen Felix ,  Mrudula Chidambar Gore

IPC: G06F7/499 ,  G06F9/30

Abstract: A method and apparatus for handling overflow conditions resulting from arithmetic operations involving floating point numbers. An indication is stored as part of a thread's context indicating one of two possible modes for handling overflow conditions. In a first mode, a result of an arithmetic operation is set to the limit representable in the floating point format. In a second mode, a result of an arithmetic operation is set to a NaN.

公开(公告)号：US12013781B2

公开(公告)日：2024-06-18

申请号：US17653012

申请日：2022-03-01

Applicant: Graphcore Limited

Inventor： Sam Chesney ,  Alan Graham Alexander ,  Richard Luke Southwell Osborne ,  Edward Andrews

IPC: G06F12/0804 ,  G06F9/30

CPC classification number: G06F12/0804 ,  G06F9/30098 ,  G06F2212/6026

Abstract: For certain applications, parts of the application data held in memory of a processing device (e.g. that are produced as a result of operations performed by the execution unit) are arranged in regular repeating patterns in the memory, and therefore, the execution unit may set up a suitable striding pattern for use by a send engine. The send engine accesses the memory at locations in accordance with the configured striding pattern so as to access a plurality of items of data that are arranged together in a regular pattern. In a similar manner as done for sends, the execution may set up a striding pattern for use by a receive engine. The receive engine, upon receiving a plurality of items of data, causes those items of data to be stored at locations in the memory, as determined in accordance with the configured striding pattern.