公开(公告)号：US20070015305A1

公开(公告)日：2007-01-18

申请号：US11181189

申请日：2005-07-13

Applicant: Jeng-Shyan Lin ,  Chien-Hsien Tseng ,  Shou-Gwo Wuu ,  Ho-Ching Chien ,  Dun-Nian Yaung ,  Hung-Jen Hsu

Inventor： Jeng-Shyan Lin ,  Chien-Hsien Tseng ,  Shou-Gwo Wuu ,  Ho-Ching Chien ,  Dun-Nian Yaung ,  Hung-Jen Hsu

IPC: H01L21/00

CPC classification number: H01L27/14685 ,  H01L27/14623 ,  H01L27/14627 ,  H01L27/14632

Abstract: A semiconductor device including a semiconductor substrate having a photosensor formed therein; a first layer overlying the substrate, the first layer includes a portion having a generally concave shaped surface being the negative shaped of a micro-lens to be formed there over; a second layer overlying the first layer, the second layer including a generally convex shaped portion vertically aligned with and mating with the generally concave shaped surface, the generally convex shaped portion being constructed and arranged to define a micro-lens positioned to cause parallel light passing through the micro-lens to converge on and strike the photosensor.

Abstract translation: 一种半导体器件，包括其中形成有光电传感器的半导体衬底; 覆盖衬底的第一层，第一层包括具有大致凹形形状的表面的部分，其为在其上形成的微透镜的负形状; 覆盖第一层的第二层，第二层包括垂直对准并与大致凹形的表面配合的大致凸形的部分，大体上凸形的部分被构造和布置以限定微透镜，定位成使得平行光通过 通过微透镜收敛并撞击光电传感器。

公开(公告)号：US07145190B2

公开(公告)日：2006-12-05

申请号：US10918417

申请日：2004-08-16

Applicant: Dun-Nian Yaung ,  Sou-Kuo Wu ,  Ho-Ching Chien ,  Chien-Hsien Tseng ,  Jeng-Shyan Lin

Inventor： Dun-Nian Yaung ,  Sou-Kuo Wu ,  Ho-Ching Chien ,  Chien-Hsien Tseng ,  Jeng-Shyan Lin

IPC: H01L27/148

CPC classification number: H01L31/103 ,  H01L27/1463 ,  H01L27/14672

Abstract: A photo sensor with pinned photodiode structure integrated with a trench isolation structure. The photo sensor includes a substrate of a first conductivity type, at least one trench in the substrate, at least one doped region of the first conductivity type, and at least one doped region of a second conductivity type. Each doped region of the first conductivity type is beneath a corresponding trench. Each doped region of the second conductivity type is sandwiched between the corresponding doped region and the substrate of the first conductivity type. No edge of any doped region of the first or second conductivity type extends to the trench corners. A method of fabricating the photo sensor is also provided.

公开(公告)号：US20060270091A1

公开(公告)日：2006-11-30

申请号：US11488611

申请日：2006-07-19

Applicant: Dun-Nian Yaung ,  Sou-Kuo Wu ,  Ho-Ching Chien ,  Chien-Hsien Tseng ,  Jeng-Shyan Lin

Inventor： Dun-Nian Yaung ,  Sou-Kuo Wu ,  Ho-Ching Chien ,  Chien-Hsien Tseng ,  Jeng-Shyan Lin

IPC: H01L21/00

CPC classification number: H01L31/103 ,  H01L27/1463 ,  H01L27/14672

Abstract: A photo sensor with pinned photodiode structure integrated with a trench isolation structure. The photo sensor includes a substrate of a first conductivity type, at least one trench in the substrate, at least one doped region of the first conductivity type, and at least one doped region of a second conductivity type. Each doped region of the first conductivity type is beneath a corresponding trench. Each doped region of the second conductivity type is sandwiched between the corresponding doped region and the substrate of the first conductivity type. No edge of any doped region of the first or second conductivity type extends to the trench corners. A method of fabricating the photo sensor is also provided.

公开(公告)号：US07123303B1

公开(公告)日：2006-10-17

申请号：US08227390

申请日：1994-04-14

Applicant: Ho-Ching Chien ,  Chun-Hui Tsai ,  Chung-Ren Lao

Inventor： Ho-Ching Chien ,  Chun-Hui Tsai ,  Chung-Ren Lao

IPC: H04N3/14

CPC classification number: H04N5/378 ,  H04N5/3728 ,  H04N5/3765

Abstract: A focal plane array in which information from the pixel forming elements is transferred into a vertical shift register and then from the last stage of the vertical shift registers row by row into a horizontal shift register is provided with a storage element and gate between each vertical register and the corresponding stage of the horizontal register. After the information currently in the storage gates has been transferred to the corresponding HCCD stages, the transfer gate is closed, and the next shift of the vertical registers begins, during a time when the vertical registers would otherwise be stopped, waiting for the multi-phase operation of the horizontal register. This time is used for usefully increasing the time for the vertical shift operation, and the clock is advantageously made slower. Alternatively, a faster frame rate can be handled by conventional clock circuits.

Abstract translation: 其中将来自像素形成元件的信息逐行传送到垂直移位寄存器，然后从垂直移位寄存器的最后一级逐行传送到水平移位寄存器的焦平面阵列设置有存储元件，并且每个垂直寄存器 和水平寄存器的相应级。 在当前在存储门中的信息已经被转移到相应的HCCD级之后，传输门被关闭，并且垂直寄存器的下一个移位开始，在垂直寄存器将停止的时间期间， 水平寄存器的相位运算。 这个时间用于有效地增加垂直移位操作的时间，有利地使时钟慢。 或者，更快的帧速率可以由传统的时钟电路来处理。

公开(公告)号：US07067891B2

公开(公告)日：2006-06-27

申请号：US10701670

申请日：2003-11-04

Applicant: Dunn-Nian Yaung ,  Shou-Gwo Wuu ,  Ho-Ching Chien ,  Yi-Shing Chang

Inventor： Dunn-Nian Yaung ,  Shou-Gwo Wuu ,  Ho-Ching Chien ,  Yi-Shing Chang

IPC: H01L27/14

CPC classification number: H01L31/02002

Abstract: Each of an elevated diode sensor optoelectronic product and a method for fabricating the elevated diode sensor optoelectronic product employs a sidewall passivation dielectric layer passivating a sidewall of a patterned conductor layer which serves as a bottom electrode for an elevated diode within the elevated diode sensor optoelectronic product. The sidewall passivation dielectric layer eliminates contact between the patterned conductor layer and an intrinsic diode material layer within the elevated diode, thus providing enhanced performance of the elevated diode sensor optoelectronic product.

Abstract translation: 升高的二极管传感器光电子产品和制造高二极管传感器光电子产品的方法中的每一个使用侧壁钝化介电层，钝化图案化导体层的侧壁，其用作升高的二极管传感器光电子产品中的升高的二极管的底部电极 。 侧壁钝化介质层消除了图案化的导体层和升高的二极管内的本征二极管材料层之间的接触，从而提高了升高的二极管传感器光电产品的性能。

公开(公告)号：US20060076580A1

公开(公告)日：2006-04-13

申请号：US11282428

申请日：2005-11-18

Applicant: Dun-Nian Yaung ,  Sou-Kuo Wu ,  Ho-Ching Chien

Inventor： Dun-Nian Yaung ,  Sou-Kuo Wu ,  Ho-Ching Chien

IPC: H01L29/76

CPC classification number: H01L27/14636 ,  H01L27/14643

Abstract: An image sensor with a vertically integrated thin-film photodiode includes a bottom doped layer of a PIN photodiode imbedded in a dielectric layer, wherein a bottom surface of the bottom doped layer completely contacts its corresponding underlying pixel electrode. The bottom doped layers of the PIN photodiodes are formed by a self-aligned and damascene method, therefore the pixel electrodes are not exposed to the I-type amorphous silicon layer of the PIN photodiodes. Moreover, the transparent electrode connects the PIN photodiodes to an external ground voltage power through a ground pad which is a portion of a top metal layer.

Abstract translation: 具有垂直集成的薄膜光电二极管的图像传感器包括嵌入在电介质层中的PIN光电二极管的底部掺杂层，其中底部掺杂层的底表面完全接触其相应的底层像素电极。 PIN光电二极管的底部掺杂层通过自对准和镶嵌方法形成，因此像素电极不暴露于PIN光电二极管的I型非晶硅层。 此外，透明电极通过作为顶部金属层的一部分的接地焊盘将PIN光电二极管连接到外部接地电压电力。

公开(公告)号：US20060063294A1

公开(公告)日：2006-03-23

申请号：US11271116

申请日：2005-11-10

Applicant: Tzu-Hsuan Hsu ,  Shou-Gwo Wuu ,  Ho-Ching Chien ,  Dun-Nian Yaung

Inventor： Tzu-Hsuan Hsu ,  Shou-Gwo Wuu ,  Ho-Ching Chien ,  Dun-Nian Yaung

IPC: H01L21/00

CPC classification number: H01L27/14632 ,  H01L27/1462

Abstract: A plurality of apertures is formed in at least one first insulating layer disposed over a sensor formed in a semiconductor substrate. A second insulating layer is disposed over the at least one first insulating layer and the plurality of apertures in the at least one first insulating layer. The apertures form hollow regions in the at least one first insulating layer over the sensor, allowing more light or energy to pass through the at least one first insulating layer to the sensor, and increasing the sensitivity of the sensor.

Abstract translation: 在设置在形成于半导体衬底中的传感器上的至少一个第一绝缘层中形成多个孔。 第二绝缘层设置在至少一个第一绝缘层和至少一个第一绝缘层中的多个孔之上。 所述孔在所述传感器上的所述至少一个第一绝缘层中形成中空区域，允许更多的光或能量穿过所述至少一个第一绝缘层到所述传感器，并且增加所述传感器的灵敏度。

公开(公告)号：US20060033127A1

公开(公告)日：2006-02-16

申请号：US10918417

申请日：2004-08-16

Applicant: Dun-Nian Yaung ,  Sou-Kuo Wu ,  Ho-Ching Chien ,  Chien-Hsien Tseng ,  Jeng-Shyan Lin

Inventor： Dun-Nian Yaung ,  Sou-Kuo Wu ,  Ho-Ching Chien ,  Chien-Hsien Tseng ,  Jeng-Shyan Lin

IPC: H01L27/148 ,  H01L31/00 ,  H01L31/06 ,  H01L31/105 ,  H01L29/768

CPC classification number: H01L31/103 ,  H01L27/1463 ,  H01L27/14672

Abstract: A photo sensor with pinned photodiode structure integrated with a trench isolation structure. The photo sensor includes a substrate of a first conductivity type, at least one trench in the substrate, at least one doped region of the first conductivity type, and at least one doped region of a second conductivity type. Each doped region of the first conductivity type is beneath a corresponding trench. Each doped region of the second conductivity type is sandwiched between the corresponding doped region and the substrate of the first conductivity type. No edge of any doped region of the first or second conductivity type extends to the trench corners. A method of fabricating the photo sensor is also provided.

公开(公告)号：US6153516A

公开(公告)日：2000-11-28

申请号：US151155

申请日：1998-09-10

Applicant: Ho-Ching Chien

Inventor： Ho-Ching Chien

IPC: H01L21/60 ,  H01L21/768 ,  H01L21/8242 ,  H01L23/485 ,  H01L23/532 ,  H01L21/4763

CPC classification number: H01L27/10888 ,  H01L21/76807 ,  H01L21/76897 ,  H01L23/485 ,  H01L23/53271 ,  H01L27/10885 ,  H01L2924/0002

Abstract: A process for forming a modified polysilicon plug structure, used to connect a bit line structure, of a semiconductor memory device, to an underlying source and drain region, of a transfer gate transistor, has been developed. The process features the formation of a dual shaped opening in an insulator layer, comprised of a wide, upper opening, overlying a narrower, lower opening, which exposes the top surface of a source and drain region. Polysilicon deposition and patterning result in the formation of the modified polysilicon plug structure, comprised of a wide polysilicon trench shape, in the upper opening in the insulator layer, and an underlying, narrower polysilicon plug, in the lower opening, in the insulator layer, with the narrow polysilicon plug contacting the underlying source and drain region. An overlying bit line structure is formed, contacting the top surface of the underlying, polysilicon trench shape, exposed in a bit line via hole.

Abstract translation: 已经开发了用于将半导体存储器件的位线结构连接到传输栅极晶体管的底层源极和漏极区域的用于形成修改的多晶硅插塞结构的工艺。 该方法的特征在于在绝缘体层中形成双重形状的开口，该绝缘体层由宽的上部开口构成，上部开口覆盖较窄的下部开口，该开口露出源极和漏极区域的顶部表面。 多晶硅沉积和图案化导致在绝缘体层的上部开口中形成由宽的多晶硅沟槽形状构成的修饰的多晶硅插塞结构，以及在绝缘体层中的下部开口中的下面更窄的多晶硅插塞， 其中窄的多晶硅插塞接触下面的源极和漏极区域。 形成一个覆盖的位线结构，与位线通孔中暴露的底层多晶硅沟槽形状的顶表面相接触。

公开(公告)号：US6037220A

公开(公告)日：2000-03-14

申请号：US121693

申请日：1998-07-24

Applicant: Ho-Ching Chien ,  Kao-Hsing Wang

Inventor： Ho-Ching Chien ,  Kao-Hsing Wang

IPC: H01L21/02 ,  H01L21/8242

CPC classification number: H01L27/10852 ,  H01L28/92

Abstract: A method of creating an STC structure, with increased surface area, needed for high density, DRAM designs, has been developed. The increased surface area, for the STC structure is obtained via use of HSG polysilicon sidewalls, and via use of a grated, top surface topography. A capping insulator layer is used as a hard mask, to allow formation of the HSG polysilicon sidewalls, on the sides of a storage node structure, without degradation to the top surface of the storage node structure, during the HSG polysilicon sidewall formation process. A second iteration features the creation of a storage node structure, with a grated, top surface topography, as well as HSG polysilicon sidewalls. The grated top surface topography, for the storage node structure, is obtained by forming crevices in the top surface of the storage node structure via a series of RIE procedures, using the HSG polysilicon features, and underlying capping insulator layer features, as an etch mask.

Abstract translation: 已经开发了一种创建高密度DRAM设计所需的具有增加的表面积的STC结构的方法。 通过使用HSG多晶硅侧壁，并且通过使用磨碎的顶表面形貌获得STC结构的增加的表面积。 在HSG多晶硅侧壁形成过程中，封装绝缘体层用作硬掩模，以允许在存储节点结构的侧面上形成HSG多晶硅侧壁，而不会降解到存储节点结构的顶表面。 第二次迭代的特征在于创建了具有磨碎的顶表面形貌以及HSG多晶硅侧壁的存储节点结构。 用于存储节点结构的磨碎的顶表面形貌是通过使用HSG多晶硅特征和基础封装绝缘体层特征的一系列RIE程序在存储节点结构的顶表面中形成缝隙而获得的，作为蚀刻掩模 。