公开(公告)号：US11256599B2

公开(公告)日：2022-02-22

申请号：US17128291

申请日：2020-12-21

Applicant: Intel Corporation

Inventor： Adarsh Chauhan ,  Jayesh Gaur ,  Franck Sala ,  Lihu Rappoport ,  Zeev Sperber ,  Adi Yoaz ,  Sreenivas Subramoney

IPC: G06F11/34 ,  G06F11/30 ,  G06F15/78 ,  G06F9/24 ,  G06F9/38

Abstract: A processor comprises a microarchitectural feature and dynamic tuning unit (DTU) circuitry. The processor executes a program for first and second execution windows with the microarchitectural feature disabled and enabled, respectively. The DTU circuitry automatically determines whether the processor achieved worse performance in the second execution window. In response to determining that the processor achieved worse performance in the second execution window, the DTU circuitry updates a usefulness state for a selected address of the program to denote worse performance. In response to multiple consecutive determinations that the processor achieved worse performance with the microarchitectural feature enabled, the DTU circuitry automatically updates the usefulness state to denote a confirmed bad state. In response to the usefulness state denoting the confirmed bad state, the DTU circuitry automatically disables the microarchitectural feature for the selected address for execution windows after the second execution window. Other embodiments are described and claimed.

公开(公告)号：US11188467B2

公开(公告)日：2021-11-30

申请号：US15717939

申请日：2017-09-28

Applicant: Intel Corporation

Inventor： Israel Diamand ,  Alaa R. Alameldeen ,  Sreenivas Subramoney ,  Supratik Majumder ,  Srinivas Santosh Kumar Madugula ,  Jayesh Gaur ,  Zvika Greenfield ,  Anant V. Nori

IPC: G06F12/00 ,  G06F12/0846 ,  G06F12/0811 ,  G06F12/128 ,  G06F12/121 ,  G06F12/0886 ,  G06F12/08

Abstract: A method is described. The method includes receiving a read or write request for a cache line. The method includes directing the request to a set of logical super lines based on the cache line's system memory address. The method includes associating the request with a cache line of the set of logical super lines. The method includes, if the request is a write request: compressing the cache line to form a compressed cache line, breaking the cache line down into smaller data units and storing the smaller data units into a memory side cache. The method includes, if the request is a read request: reading smaller data units of the compressed cache line from the memory side cache and decompressing the cache line.

公开(公告)号：US20210089448A1

公开(公告)日：2021-03-25

申请号：US16576687

申请日：2019-09-19

Applicant: Intel Corporation

Inventor： Huichu Liu ,  Tanay Karnik ,  Tejpal Singh ,  Yen-Cheng Liu ,  Lavanya Subramanian ,  Mahesh Kumashikar ,  Sri Harsha Chodav ,  Sreenivas Subramoney ,  Kaushik Vaidyanathan ,  Daniel H. Morris ,  Uygar E. Avci ,  Ian A. Young

IPC: G06F12/0804 ,  G06F11/20 ,  G06F12/0806 ,  G06F12/0866

Abstract: Described is an low overhead method and apparatus to reconfigure a pair of buffered interconnect links to operate in one of these three modes—first mode (e.g., bandwidth mode), second mode (e.g., latency mode), and third mode (e.g., energy mode). In bandwidth mode, each link in the pair buffered interconnect links carries a unique signal from source to destination. In latency mode, both links in the pair carry the same signal from source to destination, where one link in the pair is “primary” and other is called the “assist”. Temporal alignment of transitions in this pair of buffered interconnects reduces the effective capacitance of primary, thereby reducing delay or latency. In energy mode, one link in the pair, the primary, alone carries a signal, while the other link in the pair is idle. An idle neighbor on one side reduces energy consumption of the primary.

公开(公告)号：US20210089411A1

公开(公告)日：2021-03-25

申请号：US17111832

申请日：2020-12-04

Applicant: Intel Corporation

Inventor： Aravinda Prasad ,  Sreenivas Subramoney

IPC: G06F11/14 ,  G06F12/1009 ,  G06F12/109 ,  G06F12/1036

Abstract: Systems, apparatuses and methods may provide for technology that associates a unique identifier with an application, creates an entry in a metadata table, wherein the metadata table is at a fixed location in persistent system memory, populates the entry with the unique identifier, a user identifier, and a pointer to a root of a page table tree, and recovers in-use data pages after a system crash. In one example, the in-use data pages are recovered from the persistent system memory based on the metadata table and include one or more of application heap information or application stack information.

公开(公告)号：US10776270B2

公开(公告)日：2020-09-15

申请号：US16222788

申请日：2018-12-17

Applicant: Intel Corporation

Inventor： Jayesh Gaur ,  Ayan Mandal ,  Anant V. Nori ,  Sreenivas Subramoney

IPC: G06F12/0811 ,  G06F12/0804 ,  G06F12/084 ,  G06F12/0888 ,  G06F11/34

Abstract: A memory-efficient last level cache (LLC) architecture is described. A processor implementing a LLC architecture may include a processor core, a last level cache (LLC) operatively coupled to the processor core, and a cache controller operatively coupled to the LLC. The cache controller is to monitor a bandwidth demand of a channel between the processor core and a dynamic random-access memory (DRAM) device associated with the LLC. The cache controller is further to perform a first defined number of consecutive reads from the DRAM device when the bandwidth demand exceeds a first threshold value and perform a first defined number of consecutive writes of modified lines from the LLC to the DRAM device when the bandwidth demand exceeds the first threshold value.

公开(公告)号：US20200169383A1

公开(公告)日：2020-05-28

申请号：US16776467

申请日：2020-01-29

Applicant: Intel Corporation

Inventor： David M. Durham ,  Michael LeMay ,  Michael E. Kounavis ,  Santosh Ghosh ,  Sergej Deutsch ,  Anant Vithal Nori ,  Jayesh Gaur ,  Sreenivas Subramoney ,  Karanvir S. Grewal

IPC: H04L9/06 ,  G06F12/1027 ,  G06F9/30

Abstract: A processor comprises a first register to store an encoded pointer to a memory location. First context information is stored in first bits of the encoded pointer and a slice of a linear address of the memory location is stored in second bits of the encoded pointer. The processor also includes circuitry to execute a memory access instruction to obtain a physical address of the memory location, access encrypted data at the memory location, derive a first tweak based at least in part on the encoded pointer, and generate a keystream based on the first tweak and a key. The circuitry is to further execute the memory access instruction to store state information associated with memory access instruction in a first buffer, and to decrypt the encrypted data based on the keystream. The keystream is to be generated at least partly in parallel with accessing the encrypted data.

公开(公告)号：US10559348B2

公开(公告)日：2020-02-11

申请号：US15980813

申请日：2018-05-16

Applicant: Intel Corporation

Inventor： Lavanya Subramanian ,  Kaushik Vaidyanathan ,  Anant Nori ,  Sreenivas Subramoney ,  Tanay Karnik

IPC: G11C7/00 ,  G11C11/4094 ,  G06F13/16 ,  G11C11/4093 ,  G11C11/4091

Abstract: In one embodiment, an apparatus includes a memory array having a plurality of memory cells, a plurality of bitlines coupled to the plurality of memory cells, and a plurality of wordlines coupled to the plurality of memory cells. The memory array may further include a sense amplifier circuit to sense and amplify a value stored in a memory cell of the plurality of memory cells. The sense amplifier circuit may include: a buffer circuit to store the value, the buffer circuit coupled between a first internal node of the sense amplifier circuit and a second internal node of the sense amplifier circuit; and an equalization circuit to equalize the first internal node and the second internal node while the sense amplifier circuit is decoupled from the memory array. Other embodiments are described and claimed.

公开(公告)号：US20190286567A1

公开(公告)日：2019-09-19

申请号：US15923174

申请日：2018-03-16

Applicant: Intel Corporation

Inventor： Mainak Chaudhuri ,  Jayesh Gaur ,  Sreenivas Subramoney ,  Hong Wang

IPC: G06F12/0895 ,  G06F12/0891 ,  G06F12/0804 ,  G06F12/12

Abstract: In one embodiment, a processor includes: a cache memory to store a plurality of cache lines; and a cache controller to control the cache memory. The cache controller may include a control circuit to allocate a virtual write buffer within the cache memory in response to a bandwidth on an interconnect that exceeds a first bandwidth threshold. The cache controller may further include a replacement circuit to control eviction of cache lines from the cache memory. Other embodiments are described and claimed.

公开(公告)号：US10162756B2

公开(公告)日：2018-12-25

申请号：US15408731

申请日：2017-01-18

Applicant: Intel Corporation

Inventor： Jayesh Gaur ,  Ayan Mandal ,  Anant Nori ,  Sreenivas Subramoney

IPC: G06F12/08 ,  G06F12/0811

Abstract: A memory-efficient last level cache (LLC) architecture is described. A processor implementing a LLC architecture may include a processor core, a last level cache (LLC) operatively coupled to the processor core, and a cache controller operatively coupled to the LLC. The cache controller is to monitor a bandwidth demand of a channel between the processor core and a dynamic random-access memory (DRAM) device associated with the LLC. The cache controller is further to perform a first defined number of consecutive reads from the DRAM device when the bandwidth demand exceeds a first threshold value and perform a first defined number of consecutive writes of modified lines from the LLC to the DRAM device when the bandwidth demand exceeds the first threshold value.

公开(公告)号：US20180349144A1

公开(公告)日：2018-12-06

申请号：US15614757

申请日：2017-06-06

Applicant: Intel Corporation

Inventor： Rahul Pal ,  Ragavendra Natarajan ,  Niranjan K. Soundararajan ,  Sreenivas Subramoney ,  Daniel Deng ,  Jared Warner Stark, IV ,  Hong Wang ,  Ronak Singhal

IPC: G06F9/38

Abstract: In one embodiment, a processor comprises a branch predictor to generate, in association with a program loop, a frozen history vector comprising a snapshot of a branch history vector; track a current iteration of the program loop; and provide a prediction for a branch instruction associated with the program loop, the prediction based on the frozen history vector and the current iteration of the program loop.