公开(公告)号：US20240006380A1

公开(公告)日：2024-01-04

申请号：US17856830

申请日：2022-07-01

Applicant: Intel Corporation

Inventor： Suddhasattwa Nad ,  Srinivas Pietambaram ,  Rahul Manepalli ,  Marcel Wall ,  Darko Grujicic

IPC: H01L25/065 ,  H01L23/538 ,  H01L23/498 ,  H01L21/48

CPC classification number: H01L25/0655 ,  H01L23/5383 ,  H01L23/49866 ,  H01L21/4857

Abstract: High-density IC die package routing structures with one or more nitrided surfaces. Metallization features may be formed, for example with a plating process. Following the plating process, a surface of the metallization features may be exposed to a surface treatment that incorporates nitrogen onto a surface of the metallization. The presence of nitrogen may chemically improve adhesion between finely patterned metallization features and package dielectric material. Accordingly, surface roughness of metallization features may be reduced without suffering delamination. With lower surface roughness, metallization features may transmit higher frequency data signals with lower insertion loss.

公开(公告)号：US11862619B2

公开(公告)日：2024-01-02

申请号：US16649923

申请日：2017-12-29

Applicant: Intel Corporation

Inventor： Srinivas Pietambaram ,  Robert Alan May ,  Kristof Darmawikarta ,  Hiroki Tanaka ,  Rahul N. Manepalli ,  Sri Ranga Sai Boyapati

IPC: H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H01L25/00 ,  H01L21/48 ,  H01L23/00

CPC classification number: H01L25/50 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/49866 ,  H01L23/5385 ,  H01L23/5389 ,  H01L25/0652 ,  H01L24/14 ,  H01L2224/1403

Abstract: Techniques for a patch to couple one or more surface dies to an interposer or motherboard are provided. In an example, the patch can include multiple embedded dies. In an example, a microelectronic device can be formed to include a patch on an interposer, where the patch can include multiple embedded dies and each die can have a different thickness.

公开(公告)号：US11756890B2

公开(公告)日：2023-09-12

申请号：US17732365

申请日：2022-04-28

Applicant: Intel Corporation

Inventor： Srinivas Pietambaram ,  Rahul Manepalli ,  Gang Duan

IPC: H01L23/31 ,  H01L23/538 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L21/683 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L23/5381 ,  H01L21/486 ,  H01L21/4853 ,  H01L21/565 ,  H01L21/6835 ,  H01L23/3107 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/562 ,  H01L25/0652 ,  H01L25/50 ,  H01L2221/68372 ,  H01L2225/06513 ,  H01L2225/06548 ,  H01L2225/06558 ,  H01L2225/06582 ,  H01L2225/06589

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, a microelectronic device package may include a redistribution layer (RDL) and an interposer over the RDL. In an embodiment, a glass core may be formed over the RDL and surround the interposer. In an embodiment, the microelectronic device package may further comprise a plurality of dies over the interposer. In an embodiment, the plurality of dies are communicatively coupled with the interposer.

公开(公告)号：US20230092903A1

公开(公告)日：2023-03-23

申请号：US17480953

申请日：2021-09-21

Applicant: Intel Corporation

Inventor： Sameer Paital ,  Gang Duan ,  Srinivas Pietambaram ,  Yosuke Kanaoka ,  Tchefor Ndukum

IPC: H01L23/538 ,  H01L23/00 ,  H01L21/48

Abstract: Methods and apparatus to embed host dies in a substrate are disclosed An apparatus includes a first die having a first side and a second side opposite the first side. The first side includes a first contact to be electrically coupled with a second die. The second side includes a second contact. The apparatus further includes a substrate including a metal layer and a dielectric material on the metal layer. The first die is encapsulated within the dielectric material. The second contact of the first die is bonded to the metal layer independent of an adhesive.

公开(公告)号：US11574993B2

公开(公告)日：2023-02-07

申请号：US16271639

申请日：2019-02-08

Applicant: Intel Corporation

Inventor： Rengarajan Shanmugam ,  Suddhasattwa Nad ,  Darko Grujicic ,  Srinivas Pietambaram

IPC: H01L23/498 ,  H01F27/28 ,  H01L21/48 ,  H01L49/02 ,  H01L23/66 ,  H01F27/24 ,  H01L25/16 ,  H01L23/552 ,  H01F41/04 ,  H01L23/00

Abstract: Embodiments disclosed herein include electronic packages with embedded magnetic materials and methods of forming such packages. In an embodiment, the electronic package comprises a package substrate, where the package substrate comprises a plurality of dielectric layers. In an embodiment a plurality of passive components is located in a first dielectric layer of the plurality of dielectric layers. In an embodiment, first passive components of the plurality of passive components each comprise a first magnetic material, and second passive components of the plurality of passive components each comprise a second magnetic material. In an embodiment, a composition of the first magnetic material is different than a composition of the second magnetic material.

公开(公告)号：US20220285079A1

公开(公告)日：2022-09-08

申请号：US17192187

申请日：2021-03-04

Applicant: Intel Corporation

Inventor： Srinivas Pietambaram ,  Pooya Tadayon ,  Kristof Darmawikarta ,  Tarek Ibrahim ,  Prithwish Chatterjee

IPC: H01F27/28 ,  H01F1/04 ,  H01F27/40 ,  H05K1/16

Abstract: An inductor can be formed in a coreless electronic substrate from magnetic materials and/or fabrication processes that do not result in the magnetic materials leaching into plating and/or etching solutions/chemistries, and results in a unique inductor structure. This may be achieved by forming the inductors from magnetic ferrites. The formation of the electronic substrates may also include process sequences that prevent exposure of the magnetic ferrites to the plating and/or etching solutions/chemistries.

公开(公告)号：US11270959B2

公开(公告)日：2022-03-08

申请号：US15933599

申请日：2018-03-23

Applicant: Intel Corporation

Inventor： Kirstof Darmawikarta ,  Srinivas Pietambaram ,  Prithwish Chatterjee ,  Sri Ranga Sai Boyapati ,  Wei Lun Jen

IPC: H01L23/64 ,  H01F27/28 ,  H01F1/14 ,  H01F1/34 ,  H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01F41/04

Abstract: Techniques for fabricating a semiconductor package comprising inductor features and a magnetic film are described. For one technique, fabricating a package includes: forming inductor features comprising a pad and a conductive line on a first build-up layer; forming a raised pad structure on the first build-up layer by fabricating a pillar structure on the pad, wherein a size of the pillar structure is approximately equal or equal to a corresponding size of the pad such that the pillar structure and the pad are aligned or minimally misaligned relative to each other; encapsulating the inductor features and the raised pad structure in a magnetic film; planarizing the magnetic film until top surfaces of the raised pad structure and magnetic film are co-planar; depositing an additional layer on the top surfaces; and forming a via on the raised pad structure by removing portions of the additional layer above the raised pad structure.

公开(公告)号：US10856424B2

公开(公告)日：2020-12-01

申请号：US15762856

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： Sri Ranga Sai Boyapati ,  Amanda E. Schuckman ,  Sashi S. Kandanur ,  Srinivas Pietambaram ,  Mark Hlad ,  Kristof Darmawikarta

IPC: C25D3/38 ,  H05K3/42 ,  H05K3/46

Abstract: A method that includes electroplating both sides of a core and the through hole of a core with a conductive material to cover both sides of the core with the conductive material and to form a conductive bridge in the through hole, wherein the core has a thickness greater than 200 microns; etching the conductive material that covers both sides of the core to reduce the thickness of the conductive material to about 1 micron; applying a film resist to the core; exposing and developing the resist film to form patterns on the conductive material on both sides of the core; and electroplating additional conductive material on the (i) conductive material on both sides of the core (ii) conductive material within the through hole; and (iii) conductive bridge to fill the through hole with conductive material without any voids and to form conductive patterns on both sides of the core.

公开(公告)号：US10777514B2

公开(公告)日：2020-09-15

申请号：US16012371

申请日：2018-06-19

Applicant: Intel Corporation

Inventor： Cheng Xu ,  Yikang Deng ,  Kyu Oh Lee ,  Ji Yong Park ,  Srinivas Pietambaram ,  Ying Wang ,  Chong Zhang ,  Rui Zhang ,  Junnan Zhao

IPC: H01L23/64 ,  H01L23/522 ,  H01L23/528 ,  H01F27/24 ,  H01L27/04 ,  H01F27/28 ,  H01L21/822

Abstract: Techniques are provided for an inductor at a second level interface between a first substrate and a second substrate. In an example, the inductor can include a winding and a core disposed inside the winding. The winding can include first conductive traces of a first substrate, second conductive traces of a second non-semiconductor substrate, and a plurality of connectors configured to connect the first substrate with the second substrate. Each connector of the plurality of connectors can be located between a trace of the first conductive traces and a corresponding trace of the second conductive traces.

公开(公告)号：US20190312019A1

公开(公告)日：2019-10-10

申请号：US15949141

申请日：2018-04-10

Applicant: Intel Corporation

Inventor： Srinivas Pietambaram ,  Gang Duan ,  Deepak Kulkarni

IPC: H01L25/00 ,  H01L23/48 ,  H01L23/538 ,  H01L23/31 ,  H01L23/29 ,  H01L21/683

Abstract: Techniques are provided for fine node heterogeneous-chip packages. In an example, a method of making a heterogeneous-chip package can include coupling electrical terminals of a first side of a first base die to electrical terminals of a first side of a second base die using a silicon bridge, forming an organic substrate about the silicon bridge and adjacent the first sides of the first and second base dies, and coupling a fine node die to a second side of at least one of the first base die or the second base die.