公开(公告)号：US11075134B2

公开(公告)日：2021-07-27

申请号：US16556642

申请日：2019-08-30

Applicant: Infineon Technologies AG

Inventor： Markus Kahn ,  Oliver Humbel ,  Philipp Sebastian Koch ,  Angelika Koprowski ,  Christian Maier ,  Gerhard Schmidt ,  Juergen Steinbrenner

IPC: H01L23/31 ,  H01L23/29 ,  C23C16/34 ,  H01L23/00 ,  H01L21/02 ,  H01L29/06

Abstract: A semiconductor device includes a semiconductor body and a first portion including silicon and nitrogen. The first portion is in direct contact with the semiconductor body. A second portion including silicon and nitrogen is in direct contact with the first portion. The first portion is between the semiconductor body and the second portion. An average silicon content in the first portion is higher than in the second portion.

公开(公告)号：US20210151391A1

公开(公告)日：2021-05-20

申请号：US17086979

申请日：2020-11-02

Applicant: Infineon Technologies AG

Inventor： Angelika Koprowski ,  Oliver Humbel ,  Markus Kahn ,  Carsten Schaeffer

IPC: H01L23/00 ,  H01L29/40

Abstract: A high voltage semiconductor device includes a high voltage electrically conductive structure and a step topography at or in the vicinity of the high voltage electrically conductive structure. A layer stack covers the step topography. The layer stack includes an electrically insulating buffer layer, a SiC layer over the electrically insulating buffer layer and a silicon nitride layer over the SiC layer or a nitrided surface region of the SiC layer.

公开(公告)号：US10710874B2

公开(公告)日：2020-07-14

申请号：US15636702

申请日：2017-06-29

Applicant: Infineon Technologies AG

Inventor： Tobias Frischmuth ,  Guenter Denifl ,  Thomas Grille ,  Ursula Hedenig ,  Markus Kahn ,  Daniel Maurer ,  Ulrich Schmid ,  Michael Schneider

IPC: H04R19/00 ,  B81C1/00 ,  G01Q70/14 ,  H04R7/26 ,  G01L7/08 ,  G01L1/00 ,  B81B3/00 ,  G01Q60/24 ,  H04R19/02 ,  H04R7/10 ,  H04R19/04

Abstract: A micromechanical structure in accordance with various embodiments may include: a substrate; and a functional structure arranged at the substrate; wherein the functional structure includes a functional region which is deflectable with respect to the substrate responsive to a force acting on the functional region; and wherein at least a section of the functional region has an elastic modulus in the range from about 5 GPa to about 70 GPa.

公开(公告)号：US20180237292A1

公开(公告)日：2018-08-23

申请号：US15901196

申请日：2018-02-21

Applicant: Infineon Technologies AG

Inventor： Markus Kahn ,  Anna-Katharina Kaiser ,  Soenke Pirk ,  Juergen Steinbrenner ,  Julia-Magdalena Straeussnigg

IPC: B81C1/00 ,  H04R19/04 ,  H04R19/00

CPC classification number: B81C1/00801 ,  B81C2201/0133 ,  B81C2201/0176 ,  B81C2201/053 ,  B81C2201/056 ,  H04R19/005 ,  H04R19/04 ,  H04R31/00 ,  H04R2201/003

Abstract: A semiconductor device comprises a structured metal layer. The structured metal layer lies above a semiconductor substrate. In addition, a thickness of the structured metal layer is more than 100 nm. Furthermore, the semiconductor device comprises a covering layer. The covering layer lies adjacent to at least one part of a front side of the structured metal layer and adjacent to a side wall of the structured metal layer. In addition, the covering layer comprises amorphous silicon carbide.

公开(公告)号：US10049879B2

公开(公告)日：2018-08-14

申请号：US15582940

申请日：2017-05-01

Applicant: Infineon Technologies AG

Inventor： Ravi Keshav Joshi ,  Romain Esteve ,  Markus Kahn ,  Kurt Pekoll ,  Juergen Steinbrenner ,  Gerald Unegg

IPC: H01L29/15 ,  H01L21/04 ,  H01L29/16 ,  H01L21/324 ,  H01L29/45 ,  H01L21/02

Abstract: A silicon-carbide substrate that includes: a doped silicon-carbide contact region directly adjoining a main surface of the substrate, and a dielectric layer covering the main surface is provided. A protective layer is formed on the silicon-carbide substrate such that the protective layer covers the dielectric layer and exposes the doped silicon-carbide contact region at the main surface. A metal layer that conforms to the protective layer and directly contacts the exposed doped silicon-carbide contact region is deposited. A first rapid thermal anneal process is performed. A thermal budget of the first rapid thermal anneal process is selected to cause the metal layer to form a silicide with the doped silicon-carbide contact region during the first rapid thermal anneal process without causing the metal layer to form a silicide with the protective layer during the first rapid thermal anneal process.

公开(公告)号：US20170194205A1

公开(公告)日：2017-07-06

申请号：US14979200

申请日：2015-12-22

Applicant: Infineon Technologies AG

Inventor： Gudrun Stranzl ,  Martin Zgaga ,  Markus Kahn ,  Guenter Denifl

IPC: H01L21/78 ,  H01L21/02 ,  H01L21/762

CPC classification number: H01L21/78 ,  H01L21/02115 ,  H01L21/0212 ,  H01L21/308 ,  H01L21/76224 ,  H01L21/82 ,  H01L21/8258

Abstract: In one embodiment, a method of forming a semiconductor device includes forming openings in a substrate. The method includes forming a dummy fill material within the openings and thinning the substrate to expose the dummy fill material. The dummy fill material is removed.

公开(公告)号：US09666482B1

公开(公告)日：2017-05-30

申请号：US15265081

申请日：2016-09-14

Applicant: Infineon Technologies AG

Inventor： Ravi Keshav Joshi ,  Romain Esteve ,  Markus Kahn ,  Kurt Pekoll ,  Juergen Steinbrenner ,  Gerald Unegg

IPC: H01L29/15 ,  H01L21/768 ,  H01L29/16 ,  H01L29/78 ,  H01L29/10 ,  H01L29/45 ,  H01L29/66 ,  H01L21/04

CPC classification number: H01L21/0485 ,  H01L21/0217 ,  H01L21/28518 ,  H01L21/324 ,  H01L21/76897 ,  H01L29/1608 ,  H01L29/45 ,  H01L29/66068 ,  H01L29/665 ,  H01L29/7802

Abstract: A silicon-carbide substrate that includes a doped contact region and a dielectric layer is provided. A protective layer is formed on the dielectric layer. A structured mask is formed on the protective layer. Sections of the protective layer and the dielectric layer that are exposed by openings in the mask are removed. The structured mask is removed. A metal layer is deposited such that a first portion of the metal layer directly contacts the doped contact region and a second portion of the metal layer lines the remaining sections of the protective layer and the dielectric layer. A first rapid thermal anneal process is performed. After performing the first rapid thermal anneal process, the second portion of the metal layer and the remaining section of the protective layer are removed without removing the first portion of the metal layer.

公开(公告)号：US09478409B2

公开(公告)日：2016-10-25

申请号：US14594193

申请日：2015-01-12

Applicant: Infineon Technologies AG

Inventor： Juergen Steinbrenner ,  Markus Kahn ,  Helmut Schoenherr

IPC: H01L21/31 ,  H01L21/02 ,  H01L21/302 ,  C23C16/02 ,  C23C16/40

CPC classification number: H01L21/02126 ,  C23C16/0209 ,  C23C16/401 ,  H01L21/02129 ,  H01L21/02164 ,  H01L21/02271 ,  H01L21/02318 ,  H01L21/302 ,  H01L21/31 ,  H01L21/67034

Abstract: In various embodiments, a method for coating a workpiece is provided. The method may include drying a workpiece, the workpiece being coated with at least one oxide layer as an uppermost layer; depositing a dielectric layer over the uppermost layer of the dried workpiece; wherein the workpiece is continuously subject to a pressure which is lower than atmospheric pressure during the drying process and during the depositing process.

Abstract translation: 在各种实施例中，提供了一种用于涂覆工件的方法。 所述方法可以包括干燥工件，所述工件被涂覆有至少一个作为最上层的氧化物层; 在干燥工件的最上层上沉积介电层; 其中工件在干燥过程期间和沉积过程中连续经受低于大气压的压力。

公开(公告)号：US20150340224A1

公开(公告)日：2015-11-26

申请号：US14594193

申请日：2015-01-12

Applicant: Infineon Technologies AG

Inventor： Juergen Steinbrenner ,  Markus Kahn ,  Helmut Schoenherr

IPC: H01L21/02

CPC classification number: H01L21/02126 ,  C23C16/0209 ,  C23C16/401 ,  H01L21/02129 ,  H01L21/02164 ,  H01L21/02271 ,  H01L21/02318 ,  H01L21/302 ,  H01L21/31 ,  H01L21/67034

Abstract: In various embodiments, a method for coating a workpiece is provided. The method may include drying a workpiece, the workpiece being coated with at least one oxide layer as an uppermost layer; depositing a dielectric layer over the uppermost layer of the dried workpiece; wherein the workpiece is continuously subject to a pressure which is lower than atmospheric pressure during the drying process and during the depositing process.

Abstract translation: 在各种实施例中，提供了一种用于涂覆工件的方法。 所述方法可以包括干燥工件，所述工件被涂覆有至少一个作为最上层的氧化物层; 在干燥工件的最上层上沉积介电层; 其中工件在干燥过程期间和沉积过程中连续经受低于大气压的压力。