公开(公告)号：US20190235611A1

公开(公告)日：2019-08-01

申请号：US16382320

申请日：2019-04-12

Applicant: Intel Corporation

Inventor： Avinash N. Ananthakrishnan ,  Efraim Rotem ,  Eliezer Weissmann ,  Doron Rajwan ,  Nadav Shulman ,  Alon Naveh ,  Hisham Abu-Salah

IPC: G06F1/3234 ,  G06F12/0802 ,  G06F12/0864 ,  G06F1/28 ,  G06F12/084 ,  G06F1/3287 ,  G06F12/0846

CPC classification number: G06F1/3275 ,  G06F1/28 ,  G06F1/3287 ,  G06F12/0802 ,  G06F12/084 ,  G06F12/0848 ,  G06F12/0864 ,  G06F2212/1028 ,  G06F2212/282 ,  G06F2212/502 ,  G06F2212/621 ,  Y02D10/13

Abstract: In one embodiment, the present invention is directed to a processor having a plurality of cores and a cache memory coupled to the cores and including a plurality of partitions. The processor can further include a logic to dynamically vary a size of the cache memory based on a memory boundedness of a workload executed on at least one of the cores. Other embodiments are described and claimed.

公开(公告)号：US09939879B2

公开(公告)日：2018-04-10

申请号：US14875930

申请日：2015-10-06

Applicant: Intel Corporation

Inventor： Avinash N. Ananthakrishnan ,  Efraim Rotem ,  Doron Rajwan ,  Jeremy J. Shrall ,  Eric C. Samson ,  Eliezer Weissmann ,  Ryan Wells

IPC: G06F13/14 ,  G06F1/32 ,  G06F1/30 ,  G06F1/26

CPC classification number: G06F1/324 ,  G06F1/26 ,  G06F1/30 ,  G06F1/3203 ,  G06F1/3234 ,  G06F1/3243 ,  G06F13/14 ,  Y02D10/126

Abstract: In one embodiment, the present invention includes a method for determining that a non-core domain of a multi-domain processor is not operating at a frequency requested by the non-core domain, sending a request from the non-core domain to a power controller to reduce a frequency of a core domain of the multi-domain processor, and responsive to the request, reducing the core domain frequency. Other embodiments are described and claimed.

公开(公告)号：US09760409B2

公开(公告)日：2017-09-12

申请号：US15162709

申请日：2016-05-24

Applicant: Intel Corporation

Inventor： Krishnakanth V. Sistla ,  Mark Rowland ,  Ankush Varma ,  Ian M. Steiner ,  Matthew Bace ,  Daniel Borkowski ,  Vivek Garg ,  Chelsea Akturan ,  Avinash N. Ananthakrishnan

IPC: G06F1/32 ,  G06F9/50

CPC classification number: G06F9/5094 ,  G06F1/3206 ,  G06F1/3228 ,  G06F1/3234 ,  G06F1/324 ,  G06F1/3287 ,  Y02D10/126 ,  Y02D10/171

Abstract: In one embodiment, the present invention includes a multicore processor having a power controller with logic to dynamically switch a power management policy from a power biased policy to a performance biased policy when a utilization of the processor exceeds a threshold level. Thus at low utilizations, reduced power consumption can be realized, while at higher utilizations, greater performance can be realized. Other embodiments are described and claimed.

公开(公告)号：US20170097668A1

公开(公告)日：2017-04-06

申请号：US15381241

申请日：2016-12-16

Applicant: Intel Corporation

Inventor： Avinash N. Ananthakrishnan ,  Inder M. Sodhi ,  Efraim Rotem ,  Doron Rajwan ,  Eliezer Weissmann ,  Ryan Wells

IPC: G06F1/32 ,  G06F13/40

CPC classification number: G06F1/324 ,  G06F1/3203 ,  G06F1/3293 ,  G06F1/3296 ,  G06F13/4068 ,  G06F13/4282 ,  G11C7/22 ,  Y02D10/122 ,  Y02D10/126 ,  Y02D10/151

Abstract: In one embodiment, the present invention includes a processor having multiple domains including at least a core domain and a non-core domain that is transparent to an operating system (OS). The non-core domain can be controlled by a driver. In turn, the processor further includes a memory interconnect to interconnect the core domain and the non-core domain to a memory coupled to the processor. Still further, a power controller, which may be within the processor, can control a frequency of the memory interconnect based on memory boundedness of a workload being executed on the non-core domain. Other embodiments are described and claimed.

公开(公告)号：US20170083076A1

公开(公告)日：2017-03-23

申请号：US15367330

申请日：2016-12-02

Applicant: Intel Corporation

Inventor： Krishnakanth V. Sistla ,  Jeremy Shrall ,  Stephen H. Gunther ,  Efraim Rotem ,  Alon Naveh ,  Eliezer Weissmann ,  Anil Aggarwal ,  Martin T. Rowland ,  Ankush Varma ,  Ian M. Steiner ,  Matthew Bace ,  Avinash N. Ananthakrishnan ,  Jason Brandt

IPC: G06F1/32 ,  G06F1/26

CPC classification number: G06F1/3275 ,  G06F1/266 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/3234

Abstract: In one embodiment, the present invention includes a processor having a core and a power controller to control power management features of the processor. The power controller can receive an energy performance bias (EPB) value from the core and access a power-performance tuning table based on the value. Using information from the table, at least one setting of a power management feature can be updated. Other embodiments are described and claimed.

公开(公告)号：US09594560B2

公开(公告)日：2017-03-14

申请号：US14039151

申请日：2013-09-27

Applicant: Intel Corporation

Inventor： Avinash N. Ananthakrishnan ,  Stephen H. Gunther ,  Jeremy J. Shrall ,  Jay D. Schwartz

IPC: G06F1/00 ,  G06F9/30 ,  G06F11/34 ,  G06F12/08 ,  G06F9/48 ,  G06F1/32

CPC classification number: G06F9/30083 ,  G06F1/3206 ,  G06F1/324 ,  G06F1/3275 ,  G06F1/3287 ,  G06F1/3296 ,  G06F9/4893 ,  G06F11/3466 ,  G06F12/084 ,  Y02D10/126 ,  Y02D10/171 ,  Y02D10/172

Abstract: In an embodiment, a processor includes a first logic to calculate a scalability value for a processor domain based at least in part on an active state residency, a stall duration, and a memory bandwidth of the domain, and to determine an operating frequency update for the domain based at least in part on a current operating frequency of the domain and the scalability value. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，处理器包括第一逻辑，用于至少部分地基于所述域的活动状态驻留，停止持续时间和存储器带宽来计算处理器域的可扩展性值，并且确定用于 该域至少部分地基于域的当前操作频率和可扩展性值。 描述和要求保护其他实施例。

公开(公告)号：US09535487B2

公开(公告)日：2017-01-03

申请号：US14855553

申请日：2015-09-16

Applicant: Intel Corporation

Inventor： Krishnakanth V. Sistla ,  Jeremy Shrall ,  Stephen H. Gunther ,  Efraim Rotem ,  Alon Naveh ,  Eliezer Weissmann ,  Anil Aggarwal ,  Martin T. Rowland ,  Ankush Varma ,  Ian M. Steiner ,  Matthew Bace ,  Avinash N. Ananthakrishnan ,  Jason Brandt

IPC: G06F1/26 ,  G06F1/32

CPC classification number: G06F1/3275 ,  G06F1/266 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/3234

Abstract: In one embodiment, the present invention includes a processor having a core and a power controller to control power management features of the processor. The power controller can receive an energy performance bias (EPB) value from the core and access a power-performance tuning table based on the value. Using information from the table, at least one setting of a power management feature can be updated. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，本发明包括具有核心的处理器和用于控制处理器的电源管理特征的功率控制器。 功率控制器可以从核心接收能量性能偏差（EPB）值，并根据该值访问功率性能调谐表。 使用表中的信息，可以更新电源管理功能的至少一个设置。 描述和要求保护其他实施例。

公开(公告)号：US09501299B2

公开(公告)日：2016-11-22

申请号：US14306014

申请日：2014-06-16

Applicant: Intel Corporation

Inventor： Ameya Ambardekar ,  Avinash N. Ananthakrishnan ,  Ian M. Steiner

IPC: G06F1/00 ,  G06F9/445 ,  G06F1/32 ,  G06F9/48

CPC classification number: G06F9/44505 ,  G06F1/32 ,  G06F9/4893 ,  Y02D10/24

Abstract: A processor may include a cause agnostic frequency dither filter (FD filter), which may cause reduction in the frequency transitions while maintaining the performance levels. The FD Filter may minimize the performance loss, which may otherwise accrue from these frequency transitions, while trying to maximize the peak frequency of the processor. The FD filter may determine a minimum and maximum limit, which may be used by a power management unit (PMU) to restrict the number of frequency transitions to be within a specified threshold. The FD filter may determine the maximum and minimum limits based on transition data stored in internal tables captured during one or more time windows (or observation windows). Based on an average system behavior, the PMU may either apply the minimum or the maximum limit over the subsequent time window.

Abstract translation: 处理器可以包括原因不可知的频率抖动滤波器（FD滤波器），其可以导致频率转换的降低，同时保持性能水平。 在尝试使处理器的峰值频率最大化时，FD滤波器可以最小化由这些频率转换产生的性能损失。 FD滤波器可以确定最小和最大限制，其可以被功率管理单元（PMU）用来将频率转换的数量限制在规定的阈值内。 FD滤波器可以基于存储在一个或多个时间窗口（或观察窗口）中捕获的内部表格中的转换数据来确定最大和最小限制。 基于平均系统行为，PMU可以在随后的时间窗口中应用最小或最大限制。

公开(公告)号：US20160313778A1

公开(公告)日：2016-10-27

申请号：US15138505

申请日：2016-04-26

Applicant: Intel Corporation

Inventor： Avinash N. Ananthakrishnan ,  Inder M. Sodhi ,  Efraim Rotem ,  Doron Rajwan ,  Eliezer Weissmann ,  Ryan Wells

IPC: G06F1/32 ,  G06F13/42

CPC classification number: G06F1/324 ,  G06F1/3203 ,  G06F1/3293 ,  G06F1/3296 ,  G06F13/4068 ,  G06F13/4282 ,  G11C7/22 ,  Y02D10/122 ,  Y02D10/126 ,  Y02D10/151

Abstract: In one embodiment, the present invention includes a processor having multiple domains including at least a core domain and a non-core domain that is transparent to an operating system (OS). The non-core domain can be controlled by a driver. In turn, the processor further includes a memory interconnect to interconnect the core domain and the non-core domain to a memory coupled to the processor. Still further, a power controller, which may be within the processor, can control a frequency of the memory interconnect based on memory boundedness of a workload being executed on the non-core domain. Other embodiments are described and claimed.

公开(公告)号：US20140344598A1

公开(公告)日：2014-11-20

申请号：US14451807

申请日：2014-08-05

Applicant: Intel Corporation

Inventor： Avinash N. Ananthakrishnan ,  Inder M. Sodhi ,  Efraim Rotem ,  Doron Rajwan ,  Eliezer Weissmann ,  Ryan Wells

IPC: G06F1/32 ,  G11C7/22

CPC classification number: G06F1/324 ,  G06F1/3203 ,  G06F1/3293 ,  G06F1/3296 ,  G06F13/4068 ,  G06F13/4282 ,  G11C7/22 ,  Y02D10/122 ,  Y02D10/126 ,  Y02D10/151

Abstract: In one embodiment, the present invention includes a processor having multiple domains including at least a core domain and a non-core domain that is transparent to an operating system (OS). The non-core domain can be controlled by a driver. In turn, the processor further includes a memory interconnect to interconnect the core domain and the non-core domain to a memory coupled to the processor. Still further, a power controller, which may be within the processor, can control a frequency of the memory interconnect based on memory boundedness of a workload being executed on the non-core domain. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，本发明包括具有多个域的处理器，至少包括对于操作系统（OS）是透明的核心域和非核心域。 非核心域可以由驱动程序控制。 反过来，处理器还包括将核心域和非核心域互连到耦合到处理器的存储器的存储器互连。 此外，可以在处理器内的功率控制器可以基于在非核域上执行的工作负载的存储器有界性来控制存储器互连的频率。 描述和要求保护其他实施例。