公开(公告)号：US20230074199A1

公开(公告)日：2023-03-09

申请号：US17986715

申请日：2022-11-14

Applicant: Intel Corporation

Inventor： Glenn GLASS ,  Anand MURTHY ,  Biswajeet GUHA ,  Dax M. CRUM ,  Sean MA ,  Tahir GHANI ,  Susmita GHOSE ,  Stephen CEA ,  Rishabh MEHANDRU

IPC: H01L29/06 ,  H01L21/02 ,  H01L21/285 ,  H01L21/306 ,  H01L29/08 ,  H01L29/10 ,  H01L29/165 ,  H01L29/417 ,  H01L29/423 ,  H01L29/45 ,  H01L29/66 ,  H01L29/78

Abstract: Gate-all-around integrated circuit structures having vertically discrete source or drain structures, and methods of fabricating gate-all-around integrated circuit structures having vertically discrete source or drain structures, are described. For example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires. A gate stack is around the vertical arrangement of horizontal nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires, the first epitaxial source or drain structure including vertically discrete portions aligned with the vertical arrangement of horizontal nanowires. A second epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires, the second epitaxial source or drain structure including vertically discrete portions aligned with the vertical arrangement of horizontal nanowires.

公开(公告)号：US20230058558A1

公开(公告)日：2023-02-23

申请号：US17982459

申请日：2022-11-07

Applicant: Intel Corporation

Inventor： Cory BOMBERGER ,  Anand MURTHY ,  Mark T. BOHR ,  Tahir GHANI ,  Biswajeet GUHA

IPC: H01L29/08 ,  H01L29/66 ,  H01L29/78 ,  H01L29/417 ,  H01L29/423

Abstract: Gate-all-around integrated circuit structures having source or drain structures with epitaxial nubs, and methods of fabricating gate-all-around integrated circuit structures having source or drain structures with epitaxial nubs, are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires and a second vertical arrangement of horizontal nanowires. A first pair of epitaxial source or drain structures includes vertically discrete portions aligned with the first vertical arrangement of horizontal nanowires. A second pair of epitaxial source or drain structures includes vertically discrete portions aligned with the second vertical arrangement of horizontal nanowires. A conductive contact structure is laterally between and in contact with the one of the first pair of epitaxial source or drain structures and the one of the second pair of epitaxial source or drain structures.

公开(公告)号：US20230043665A1

公开(公告)日：2023-02-09

申请号：US17968558

申请日：2022-10-18

Applicant: Intel Corporation

Inventor： Cory BOMBERGER ,  Anand MURTHY ,  Stephen CEA ,  Biswajeet GUHA ,  Anupama BOWONDER ,  Tahir GHANI

IPC: H01L27/088 ,  H01L29/08 ,  H01L29/06 ,  H01L29/267

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, integrated circuit structures having channel structures with sub-fin dopant diffusion blocking layers are described. In an example, an integrated circuit structure includes a fin having a lower fin portion and an upper fin portion. The lower fin portion includes a dopant diffusion blocking layer on a first semiconductor layer doped to a first conductivity type. The upper fin portion includes a portion of a second semiconductor layer, the second semiconductor layer on the dopant diffusion blocking layer. An isolation structure is along sidewalls of the lower fin portion. A gate stack is over a top of and along sidewalls of the upper fin portion, the gate stack having a first side opposite a second side. A first source or drain structure at the first side of the gate stack.

公开(公告)号：US20220416027A1

公开(公告)日：2022-12-29

申请号：US17357664

申请日：2021-06-24

Applicant: Intel Corporation

Inventor： William HSU ,  Biswajeet GUHA ,  Chung-Hsun LIN ,  Anand S. MURTHY ,  Tahir GHANI

IPC: H01L29/08 ,  H01L29/06 ,  H01L29/786 ,  H01L29/423

Abstract: Gate-all-around integrated circuit structures having nanoribbon sub-fin isolation by backside Si substrate removal etch selective to source and drain epitaxy, are described. For example, an integrated circuit structure includes a plurality of horizontal nanowires above a sub-fin. A gate stack is over the plurality of nanowires and the sub-fin. Epitaxial source or drain structures are on opposite ends of the plurality of horizontal nanowires; and a doped nucleation layer at a base of the epitaxial source or drain structures adjacent to the sub-fin. Where the integrated circuit structure comprises an NMOS transistor, doped nucleation layer comprises a carbon-doped nucleation layer. Where the integrated circuit structure comprises a PMOS transistor, doped nucleation layer comprises a heavy boron-doped nucleation layer.

公开(公告)号：US20220415890A1

公开(公告)日：2022-12-29

申请号：US17359320

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Mohammad HASAN ,  Biswajeet GUHA ,  Oleg GOLONZKA ,  Leonard P. GULER ,  Leah SHOER ,  Daniel G. OUELLETTE ,  Pedro FRANCO NAVARRO ,  Tahir GHANI

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/78

Abstract: Integrated circuit structures having metal gates with tapered plugs, and methods of fabricating integrated circuit structures having metal gates with tapered plugs, are described. For example, includes a fin having a portion protruding above a shallow trench isolation (STI) structure. A gate dielectric material layer is over the protruding portion of the fin and over the STI structure. A conductive gate layer is over the gate dielectric material layer. A conductive gate fill material is over the conductive gate layer. A dielectric gate plug is laterally spaced apart from the fin. The dielectric gate plug is on the STI structure, and the dielectric gate plug has sides tapered outwardly from a top of the dielectric gate plug to a bottom of the dielectric gate plug.

公开(公告)号：US20220392898A1

公开(公告)日：2022-12-08

申请号：US17340429

申请日：2021-06-07

Applicant: Intel Corporation

Inventor： Tahir GHANI ,  Mohit K. HARAN ,  Mohammad HASAN ,  Biswajeet GUHA ,  Alison V. DAVIS ,  Leonard P. GULER

IPC: H01L27/092 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66

Abstract: Integrated circuit structures having cut metal gates, and methods of fabricating integrated circuit structures having cut metal gates, are described. For example, an integrated circuit structure includes a fin having a portion protruding above a shallow trench isolation (STI) structure. A gate dielectric material layer is over the protruding portion of the fin and over the STI structure. A conductive gate layer is over the gate dielectric material layer. A conductive gate fill material is over the conductive gate layer. A dielectric gate plug is laterally spaced apart from the fin, the dielectric gate plug on but not through the STI structure. The gate dielectric material layer and the conductive gate layer are not along sides of the dielectric gate plug, and the conductive gate fill material is in contact with the sides of the dielectric gate plug.

公开(公告)号：US20220344519A1

公开(公告)日：2022-10-27

申请号：US17860056

申请日：2022-07-07

Applicant: Intel Corporation

Inventor： Ayan KAR ,  Saurabh MORARKA ,  Carlos NIEVA-LOZANO ,  Kalyan KOLLURU ,  Biswajeet GUHA ,  Chung-Hsun LIN ,  Brian GREENE ,  Tahir GHANI

IPC: H01L29/93 ,  H01L29/06 ,  H01L29/66 ,  H01L21/02

Abstract: Gate-all-around integrated circuit structures including varactors are described. For example, an integrated circuit structure includes a varactor structure on a semiconductor substrate. The varactor structure includes a plurality of discrete vertical arrangements of horizontal nanowires. A plurality of gate stacks is over and surrounding corresponding ones of the plurality of discrete vertical arrangements of horizontal nanowires. The integrated circuit structure also includes a tap structure adjacent to the varactor structure on the semiconductor substrate. The tap structure includes a plurality of merged vertical arrangements of horizontal nanowires. A plurality of semiconductor structures is over and surrounding corresponding ones of the plurality of merged vertical arrangements of horizontal nanowires.

公开(公告)号：US20220320085A1

公开(公告)日：2022-10-06

申请号：US17846439

申请日：2022-06-22

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Biswajeet GUHA ,  Tahir GHANI ,  Swaminathan SIVAKUMAR

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

Abstract: Neighboring gate-all-around integrated circuit structures having disjoined epitaxial source or drain regions, and methods of fabricating neighboring gate-all-around integrated circuit structures having disjoined epitaxial source or drain regions, are described. For example, a structure includes first and second vertical arrangements of nanowires, the nanowires of the second vertical arrangement of nanowires having a horizontal width greater than a horizontal width of the nanowires of the first vertical arrangement of nanowires. First and second gate stacks are over the first and second vertical arrangements of nanowires, respectively. First epitaxial source or drain structures are at ends of the first vertical arrangement of nanowires, and second epitaxial source or drain structures are at ends of the second vertical arrangement of nanowires. An intervening dielectric structure is between neighboring ones of the first epitaxial source or drain structures and of the second epitaxial source or drain structures.

公开(公告)号：US20220199610A1

公开(公告)日：2022-06-23

申请号：US17131616

申请日：2020-12-22

Applicant: Intel Corporation

Inventor： Biswajeet GUHA ,  Brian GREENE ,  Daniel SCHULMAN ,  William HSU ,  Chung-Hsun LIN ,  Curtis TSAI ,  Kevin FISCHER

IPC: H01L27/02 ,  H01L23/60 ,  H01L29/87

Abstract: Substrate-less electrostatic discharge (ESD) integrated circuit structures, and methods of fabricating substrate-less electrostatic discharge (ESD) integrated circuit structures, are described. For example, a substrate-less integrated circuit structure includes a first fin and a second fin protruding from a semiconductor pedestal. An N-type region is in the first and second fins. A P-type region is in the semiconductor pedestal. A P/N junction is between the N-type region and the P-type region, the P/N junction on or in the semiconductor pedestal.

公开(公告)号：US20220102557A1

公开(公告)日：2022-03-31

申请号：US17549827

申请日：2021-12-13

Applicant: Intel Corporation

Inventor： Biswajeet GUHA ,  William HSU ,  Leonard P. GULER ,  Dax M. CRUM ,  Tahir GHANI

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/8234 ,  H01L23/522 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423

Abstract: Self-aligned gate endcap (SAGE) architectures with gate-all-around devices, and methods of fabricating self-aligned gate endcap (SAGE) architectures with gate-all-around devices, are described. In an example, an integrated circuit structure includes a semiconductor fin above a substrate and having a length in a first direction. A nanowire is over the semiconductor fin. A gate structure is over the nanowire and the semiconductor fin, the gate structure having a first end opposite a second end in a second direction, orthogonal to the first direction. A pair of gate endcap isolation structures is included, where a first of the pair of gate endcap isolation structures is spaced equally from a first side of the semiconductor fin as a second of the pair of gate endcap isolation structures is spaced from a second side of the semiconductor fin.