公开(公告)号：US20220415880A1

公开(公告)日：2022-12-29

申请号：US17357739

申请日：2021-06-24

Applicant: Intel Corporation

Inventor： Ayan KAR ,  Kalyan KOLLURU ,  Nicholas THOMSON ,  Rui MA ,  Benjamin ORR ,  Nathan JACK ,  Mauro KOBRINSKY ,  Patrick MORROW ,  Chung-Hsun LIN

IPC: H01L27/02

Abstract: Substrate-less diode, bipolar and feedthrough integrated circuit structures, and methods of fabricating substrate-less diode, bipolar and feedthrough integrated circuit structures, are described. For example, a substrate-less integrated circuit structure includes a semiconductor structure. A plurality of gate structures is over the semiconductor structure. A plurality of P-type epitaxial structures is over the semiconductor structure. A plurality of N-type epitaxial structures is over the semiconductor structure. One or more open locations is between corresponding ones of the plurality of gate structures. A backside contact is connected directly to one of the pluralities of P-type and N-type epitaxial structures.

公开(公告)号：US20210193836A1

公开(公告)日：2021-06-24

申请号：US16719222

申请日：2019-12-18

Applicant: Intel Corporation

Inventor： Biswajeet GUHA ,  William HSU ,  Chung-Hsun LIN ,  Kinyip PHOA ,  Oleg GOLONZKA ,  Ayan KAR ,  Nicholas THOMSON ,  Benjamin ORR ,  Nathan JACK ,  Kalyan KOLLURU ,  Tahir GHANI

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/417 ,  H01L29/06

Abstract: Gate-all-around integrated circuit structures having devices with channel-to-substrate electrical contact are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires above a first fin. A channel region of the first vertical arrangement of horizontal nanowires is electrically coupled to the first fin by a semiconductor material layer directly between the first vertical arrangement of horizontal nanowires and the first fin. A first gate stack is over the first vertical arrangement of horizontal nanowires. A second vertical arrangement of horizontal nanowires is above a second fin. A channel region of the second vertical arrangement of horizontal nanowires is electrically isolated from the second fin. A second gate stack is over the second vertical arrangement of horizontal nanowires.

公开(公告)号：US20240178273A1

公开(公告)日：2024-05-30

申请号：US18072559

申请日：2022-11-30

Applicant: Intel Corporation

Inventor： Chiao-Ti HUANG ,  Tao CHU ,  Guowei XU ,  Chung-Hsun LIN ,  Brian Greene

IPC: H01L29/06 ,  H01L23/48 ,  H01L27/088 ,  H01L29/417 ,  H01L29/786

CPC classification number: H01L29/0673 ,  H01L23/481 ,  H01L27/0886 ,  H01L29/41733 ,  H01L29/78696

Abstract: Integrated circuit structures having source or drain contacts with enhanced contact area, and methods of fabricating integrated circuit structures having source or drain contacts with enhanced contact area, are described. For example, an integrated circuit structure includes a plurality of horizontally stacked nanowires. A gate structure is over the plurality of horizontally stacked nanowires. An epitaxial source or drain structure is at an end of the plurality of horizontally stacked nanowires. A conductive contact structure is vertically over the epitaxial source or drain structure. The conductive contact structure has a lower portion extending over the top and along upper portions of sides of the epitaxial source or drain structure, and has an upper portion on the lower portion. The upper portion has a maximum lateral width less than a maximum lateral width of the lower portion.

公开(公告)号：US20240055497A1

公开(公告)日：2024-02-15

申请号：US18383370

申请日：2023-10-24

Applicant: Intel Corporation

Inventor： Biswajeet GUHA ,  William HSU ,  Chung-Hsun LIN ,  Kinyip PHOA ,  Oleg GOLONZKA ,  Tahir GHANI ,  Kalyan KOLLURU ,  Nathan JACK ,  Nicholas THOMSON ,  Ayan KAR ,  Benjamin ORR

IPC: H01L29/417 ,  H01L25/18 ,  H01L27/088 ,  H01L29/06 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/41791 ,  H01L25/18 ,  H01L27/0886 ,  H01L29/0673 ,  H01L29/401 ,  H01L29/42392 ,  H01L29/6653 ,  H01L29/6681 ,  H01L29/7853 ,  H01L2029/7858

Abstract: Gate-all-around integrated circuit structures having adjacent deep via substrate contact for sub-fin electrical contact are described. For example, an integrated circuit structure includes a conductive via on a semiconductor substrate. A vertical arrangement of horizontal nanowires is above a fin protruding from the semiconductor substrate. A channel region of the vertical arrangement of horizontal nanowires is electrically isolated from the fin. The fin is electrically coupled to the conductive via. A gate stack is over the vertical arrangement of horizontal nanowires.

公开(公告)号：US20220416022A1

公开(公告)日：2022-12-29

申请号：US17357767

申请日：2021-06-24

Applicant: Intel Corporation

Inventor： Nicholas THOMSON ,  Kalyan KOLLURU ,  Ayan KAR ,  Rui MA ,  Benjamin ORR ,  Nathan JACK ,  Biswajeet GUHA ,  Brian GREENE ,  Lin HU ,  Chung-Hsun LIN ,  Sabih OMAR

IPC: H01L29/06 ,  H01L29/423 ,  H01L27/12

Abstract: Substrate-less nanowire-based lateral diode integrated circuit structures, and methods of fabricating substrate-less nanowire-based lateral diode integrated circuit structures, are described. For example, a substrate-less integrated circuit structure includes a stack of nanowires. A plurality of P-type epitaxial structures is over the stack of nanowires. A plurality of N-type epitaxial structures is over the stack of nanowires. One or more gate structures is over the stack of nanowires. A semiconductor material is between and in contact with vertically adjacent ones of the stack of nanowires.

公开(公告)号：US20220102385A1

公开(公告)日：2022-03-31

申请号：US17033418

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Biswajeet GUHA ,  Brian GREENE ,  Avyaya JAYANTHINARASIMHAM ,  Ayan KAR ,  Benjamin ORR ,  Chung-Hsun LIN ,  Curtis TSAI ,  Kalyan KOLLURU ,  Kevin FISCHER ,  Lin HU ,  Nathan JACK ,  Nicholas THOMSON ,  Rishabh MEHANDRU ,  Rui MA ,  Sabih OMAR

IPC: H01L27/12

Abstract: Substrate-free integrated circuit structures, and methods of fabricating substrate-free integrated circuit structures, are described. For example, a substrate-less integrated circuit structure includes a fin, a plurality of gate structures over the fin, and a plurality of alternating P-type epitaxial structures and N-type epitaxial structures between adjacent ones of the plurality of gate structures.

公开(公告)号：US20210202478A1

公开(公告)日：2021-07-01

申请号：US16727336

申请日：2019-12-26

Applicant: Intel Corporation

Inventor： Biswajeet GUHA ,  William HSU ,  Michael HARPER ,  Leonard P. GULER ,  Oleg GOLONZKA ,  Dax M. CRUM ,  Chung-Hsun LIN ,  Tahir GHANI

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/786 ,  H01L29/423 ,  H01L29/08

Abstract: Gate-all-around integrated circuit structures having low aspect ratio isolation structures and subfins, and method of fabricating gate-all-around integrated circuit structures having low aspect ratio isolation structures and subfins, are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires above a first subfin. A second vertical arrangement of horizontal nanowires is above a second subfin laterally adjacent the first subfin. An isolation structure is laterally between the first subfin and the second subfin, the isolation structure having a maximum height and a maximum width with a maximum height to maximum width ratio of less than 3:1.

公开(公告)号：US20210184014A1

公开(公告)日：2021-06-17

申请号：US16716907

申请日：2019-12-17

Applicant: Intel Corporation

Inventor： Biswajeet GUHA ,  William HSU ,  Chung-Hsun LIN ,  Kinyip PHOA ,  Oleg GOLONZKA ,  Tahir GHANI

IPC: H01L29/423 ,  H01L27/088 ,  H01L29/786 ,  H01L29/417

Abstract: Gate-all-around integrated circuit structures having adjacent structures for sub-fin electrical contact are described. For example, an integrated circuit structure includes a semiconductor island on a semiconductor substrate. A vertical arrangement of horizontal nanowires is above a fin protruding from the semiconductor substrate. A channel region of the vertical arrangement of horizontal nanowires is electrically isolated from the fin. The fin is electrically coupled to the semiconductor island. A gate stack is over the vertical arrangement of horizontal nanowires.

公开(公告)号：US20250113595A1

公开(公告)日：2025-04-03

申请号：US18374607

申请日：2023-09-28

Applicant: Intel Corporation

Inventor： Tao CHU ,  Minwoo JANG ,  Yanbin LUO ,  Paul PACKAN ,  Guowei XU ,  Chiao-Ti HUANG ,  Robin CHAO ,  Feng ZHANG ,  Ting-Hsiang HUNG ,  Chia-Ching LIN ,  Yang ZHANG ,  Chung-Hsun LIN ,  Anand S. MURTHY

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

Abstract: Multiple voltage threshold integrated circuit structures with local layout effect tuning, and methods of fabricating multiple voltage threshold integrated circuit structures with local layout effect tuning, are described. For example, an integrated circuit structure includes a first fin structure or vertical arrangement of horizontal nanowires. A second fin structure or vertical arrangement of horizontal nanowires is laterally spaced apart from the first fin structure or vertical arrangement of horizontal nanowires. An N-type gate structure is over the first fin structure or vertical arrangement of horizontal nanowires. A P-type gate structure is over the second fin structure or vertical arrangement of horizontal nanowires, the P-type gate structure in contact with the N-type gate structure with a PN boundary between the P-type gate structure and the N-type gate structure. The PN boundary is offset from a central location between the first fin structure or vertical arrangement of horizontal nanowires and the second fin structure or vertical arrangement of horizontal nanowires.

公开(公告)号：US20250107175A1

公开(公告)日：2025-03-27

申请号：US18372506

申请日：2023-09-25

Applicant: Intel Corporation

Inventor： Tao CHU ,  Minwoo JANG ,  Yanbin LUO ,  Paul PACKAN ,  Guowei XU ,  Chiao-Ti HUANG ,  Robin CHAO ,  Feng ZHANG ,  Ting-Hsiang HUNG ,  Chia-Ching LIN ,  Yang ZHANG ,  Chung-Hsun LIN ,  Anand S. MURTHY

IPC: H01L29/06 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

Abstract: Integrated circuit structures having reduced local layout effects, and methods of fabricating integrated circuit structures having reduced local layout effects, are described. For example, an integrated circuit structure includes an NMOS region including a first plurality of fin structures or vertical stacks of horizontal nanowires, and first alternating gate lines and trench contact structures over the first plurality of fin structures or vertical stacks of horizontal nanowires. The integrated circuit structure also includes a PMOS region including a second plurality of fin structures or vertical stacks of horizontal nanowires, and second alternating gate and trench contact structures over the second plurality of fin structures or vertical stacks of horizontal nanowires. A gate line is shared between the NMOS region and the PMOS region, and a trench contact structure is shared between the NMOS region and the PMOS region. Ends of the gate line shared between the NMOS region and the PMOS region are offset from ends of the trench contact structure shared between the NMOS region and the PMOS region.