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公开(公告)号：US20190098764A1
公开(公告)日：2019-03-28
申请号：US16081487
申请日：2016-04-02
Applicant: INTEL CORPORATION
Inventor： ERIC LI , Kemal Aygun , Kai Xiao , Gong Ouyang , Zhichao Zhang
Abstract: Fine feature formation techniques for printed circuit boards are described. In one embodiment, for example, a method may comprise fabricating a conductive structure 306 on a low density interconnect (LDI) printed circuit board (PCB) 150 according to an LDI fabrication process and forming one or more fme conductive features on the LDI PCB by performing a fme feature formation (FFF) process, the FFF process to comprise removing conductive material of the conductive structure along an excision path to form a fme gap region 308 within the conductive structure. Other embodiments are described and claimed.
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公开(公告)号：US20180300903A1
公开(公告)日：2018-10-18
申请号：US15489068
申请日：2017-04-17
Applicant: Intel Corporation
Inventor： John G. Gierach , Hugues Labbe , Tomer Bar-On , Adam T. Lake , Kai Xiao , Ankur N. Shah , Philip R. Laws , Devan Burke , Abhishek R. Appu , Peter L. Doyle , Elmoustapha Ould-Ahmed-Vall , Travis T. Schluessler , Altug Koker
Abstract: Systems, apparatuses, and methods may provide for technology to render and compress stereoscopic graphical data. In one example, the technology identifies, from graphical data associated with a stereoscopic image defined by a first perspective view and a second perspective view, a background region and a foreground region of a graphical scene in the stereoscopic image, renders graphical data of the identified background region for the first perspective view, and compresses the rendered graphical data.
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公开(公告)号：US20180300098A1
公开(公告)日：2018-10-18
申请号：US15489096
申请日：2017-04-17
Applicant: Intel Corporation
Inventor： Deepak S. Vembar , Atsuo Kuwahara , Chandrasekaran Sakthivel , Radhakrishnan Venkataraman , Brent E. Insko , Anupreet S. Kalra , Hugues Labbe , Altug Koker , Michael Apodaca , Kai Xiao , Jeffery S. Boles , Adam T. Lake , David M. Cimini , Balaji Vembu , Elmoustapha Ould-Ahmed-Vall , Jacek Kwiatkowski , Philip R. Laws , Ankur N. Shah , Abhishek R. Appu , Joydeep Ray , Wenyin Fu , Nikos Kaburlasos , Prasoonkumar Surti , Bhushan M. Borole
Abstract: An embodiment of a graphics apparatus may include a processor, memory communicatively coupled to the processor, and a collaboration engine communicatively coupled to the processor to identify a shared graphics component between two or more users in an environment, and share the shared graphics components with the two or more users in the environment. Embodiments of the collaboration engine may include one or more of a centralized sharer, a depth sharer, a shared preprocessor, a multi-port graphics subsystem, and a decode sharer. Other embodiments are disclosed and claimed.
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公开(公告)号：US20180285109A1
公开(公告)日：2018-10-04
申请号：US15477012
申请日：2017-04-01
Applicant: Intel Corporation
Inventor： Altug Koker , Michael Apodaca , Kai Xiao , Chandrasekaran Sakthivel , Jeffery S. Boles , Adam T. Lake , Abhishek R. Appu
Abstract: Systems, apparatuses and methods may provide for technology that activates a first context on a graphics processor and detects a context switch condition with respect to the first context. Additionally, a second context may be activated, in response to the context switch condition, on the graphics processor while the first context is active on the graphics processor. In one example, activating the second context includes adding a group identifier to a plurality of threads corresponding to the second context and launching the plurality of threads with the group identifier on the graphics processor.
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公开(公告)号：US09894752B2
公开(公告)日：2018-02-13
申请号：US14678714
申请日：2015-04-03
Applicant: Intel Corporation
Inventor： Zhichao Zhang , Gong Ouyang , Kai Xiao , Kemal Aygun , Beom-Taek Lee
CPC classification number: H05K1/0237 , H01F17/0013 , H01F2017/002 , H05K1/0233 , H05K1/116 , H05K1/165
Abstract: Systems, apparatuses, and methods may include a circuit board having a plated through hole with a via portion and a stub portion and a self-coupled inductor electrically coupled to the via portion of the plated through hole. The self-coupled inductor may include a first inductor mutually coupled to a second inductor in series to reduce a capacitive effect of the stub portion of the plated through hole.
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Patent Agency Ranking
公开(公告)号：US20170310404A1
公开(公告)日：2017-10-26
申请号：US15421192
申请日：2017-01-31
Applicant: Intel Corporation
Inventor： Kai Xiao
CPC classification number: H04B3/48 , G01R35/005 , H04B3/46 , H04B17/102 , H04B17/103 , H04B17/104 , H04B17/15
Abstract: Technologies for determining the parameters of a transmission line such as a printed circuit board trace and a cable are disclosed. By measuring a reflection coefficient and a transmission coefficient of two different electrical structures with the same type of fixture on each end and transmission lines of different lengths, the attenuation coefficient of the transmission lines can be determined. The attenuation coefficient can indicate whether or not the performance of the transmission line is acceptable or may be used to calibrate a measuring device for subsequent measurements.
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37.发明授权公开(公告)号：US09338882B2
公开(公告)日：2016-05-10
申请号：US14278330
申请日：2014-05-15
Applicant: Intel Corporation
Inventor： Kai Xiao , Raul Enriquez Shibayama , Gong Ouyang
CPC classification number: H05K1/0245 , B33Y10/00 , B33Y80/00 , H01P3/02 , H01P3/08 , H01P11/003 , H05K2201/09281 , Y10T29/49156
Abstract: A broadside coupled differential design is described herein. The design may include a differential pair. Each trace of the differential pair includes a wide portion and a narrow portion. The wide portion of the first trace of the differential pair is to be aligned with a narrow portion of the second trace of the differential pair. Additionally, the wide portion of the second trace of the differential pair is to be aligned with a narrow portion of the first trace of the differential pair, such that the wide and narrow portions of the traces of the differential pair are staggered.
Abstract translation: 这里描述了宽边耦合差分设计。 该设计可以包括差分对。 差分对的每个迹线包括宽部分和窄部分。 差分对的第一迹线的宽部分将与差分对的第二迹线的窄部分对准。 此外，差分对的第二迹线的宽部分将与差分对的第一迹线的窄部分对齐，使得差分对的迹线的宽和窄部分交错。
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38.发明授权公开(公告)号：US09131603B2
公开(公告)日：2015-09-08
申请号：US13844761
申请日：2013-03-15
Applicant: INTEL CORPORATION
Inventor： Kai Xiao , Jimmy Hsu , Yuan-Liang Li , Richard K. Kunze
CPC classification number: H05K1/0228 , H01P3/08 , H01P11/00 , H05K1/0245 , H05K1/0298 , H05K2201/09236 , H05K2201/09709 , Y10T29/49155
Abstract: A signal line design is described herein. A circuit board may include a first signal line and a second signal line. The first signal line includes a pair of signal lines at a first depth of a section of a circuit board, wherein a centerline extends lengthwise between the pair of signal lines. The second signal line is disposed at a second depth of the circuit board. The second signal line includes a first segment that runs parallel to the first signal line at a first displacement from the center line. The second signal line includes a second segment that runs parallel to the first signal line on the other side of the center line at a second displacement distance from the center line.
Abstract translation: 这里描述了信号线设计。 电路板可以包括第一信号线和第二信号线。 第一信号线包括在电路板的一部分的第一深度处的一对信号线，其中中心线在该对信号线之间纵向延伸。 第二信号线设置在电路板的第二深度处。 第二信号线包括第一段，该第一段在与中心线的第一位移处平行于第一信号线延伸。 第二信号线包括与中心线的另一侧平行于第一信号线的第二段，距中心线的第二位移距离。
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公开(公告)号：US12236519B2
公开(公告)日：2025-02-25
申请号：US18090810
申请日：2022-12-29
Applicant: INTEL CORPORATION
Inventor： Karthik Vaidyanathan , Michael Apodaca , Thomas Raoux , Carsten Benthin , Kai Xiao , Carson Brownlee , Joshua Barczak
Abstract: An apparatus and method to execute ray tracing instructions. For example, one embodiment of an apparatus comprises execution circuitry to execute a dequantize instruction to convert a plurality of quantized data values to a plurality of dequantized data values, the dequantize instruction including a first source operand to identify a plurality of packed quantized data values in a source register and a destination operand to identify a destination register in which to store a plurality of packed dequantized data values, wherein the execution circuitry is to convert each packed quantized data value in the source register to a floating point value, to multiply the floating point value by a first value to generate a first product and to add the first product to a second value to generate a dequantized data value, and to store the dequantized data value in a packed data element location in the destination register.
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公开(公告)号：US12229870B2
公开(公告)日：2025-02-18
申请号：US17982766
申请日：2022-11-08
Applicant: INTEL CORPORATION
Inventor： Michael Apodaca , Carsten Benthin , Kai Xiao , Carson Brownlee , Timothy Rowley , Joshua Barczak , Travis Schluessler
Abstract: Apparatus and method for acceleration data structure refit. For example, one embodiment of an apparatus comprises: a ray generator to generate a plurality of rays in a first graphics scene; a hierarchical acceleration data structure generator to construct an acceleration data structure comprising a plurality of hierarchically arranged nodes including inner nodes and leaf nodes stored in a memory in a depth-first search (DFS) order; traversal hardware logic to traverse one or more of the rays through the acceleration data structure; intersection hardware logic to determine intersections between the one or more rays and one or more primitives within the hierarchical acceleration data structure; a node refit unit comprising circuitry and/or logic to read consecutively through at least the inner nodes in the memory in reverse DFS order to perform a bottom-up refit operation on the hierarchical acceleration data structure.
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