公开(公告)号：US11653441B2

公开(公告)日：2023-05-16

申请号：US16951695

申请日：2020-11-18

Applicant: STMicroelectronics (Alps) SAS ,  STMicroelectronics (Grenoble 2) SAS

Inventor： Julien Didion ,  Thierry Lapergue

IPC: H05K1/02 ,  H04B1/16 ,  H05K1/18

CPC classification number: H05K1/025 ,  H04B1/16 ,  H05K1/181 ,  H05K2201/09272 ,  H05K2201/09281 ,  H05K2201/10045 ,  H05K2201/10098

Abstract: A device includes a printed circuit board substrate, an antenna connected to the printed circuit board substrate, an amplifier connected to the printed circuit board substrate, and a matching track having a first end electrically connected to an input of the amplifier and a second end electrically connected to an output of the antenna. The matching track has an outgrowth that is symmetrical along a median axis of the outgrowth. The matching track is rectilinear and has a constant width over an initial part extending between the widening area and the first end. A median axis of the initial part and the median axis of the outgrowth form an angle comprised between 60 and 120°.

公开(公告)号：US09985600B2

公开(公告)日：2018-05-29

申请号：US15088147

申请日：2016-04-01

Applicant: FOXCONN INTERCONNECT TECHNOLOGY LIMITED

Inventor： Yong-Chun Xu ,  Jian-She Hu ,  Chao-Tung Huang ,  Chih-Ching Hsu

IPC: H03H7/09 ,  H01F30/02 ,  H01F27/24 ,  H01F27/28 ,  H05K1/11 ,  H01F27/29 ,  H05K1/02

CPC classification number: H03H7/09 ,  H01F27/24 ,  H01F27/28 ,  H01F27/29 ,  H01F27/292 ,  H01F30/02 ,  H05K1/0231 ,  H05K1/0233 ,  H05K1/0245 ,  H05K1/111 ,  H05K2201/09272 ,  H05K2201/09281 ,  H05K2201/10015 ,  H05K2201/1003

Abstract: A printed circuit board assembly includes a printed circuit board, a number of electronic components mounted thereon, and a number of conductive traces electrically connecting the components to form a number of transmission channels. Each of the channels has first and second transmission routes for transmitting differential signals. Each channel includes a common mode choke, a pair of capacitors, and an autotransformer. The common mode choke includes a first coil series connection with the first transmission route and a second coil series connection with the second transmission route. The capacitors include a first capacitor series connection with the first transmitting route and a second capacitor series connection with the second transmitting route.

公开(公告)号：US09504142B2

公开(公告)日：2016-11-22

申请号：US14629697

申请日：2015-02-24

Applicant: YAZAKI CORPORATION

Inventor： Hisashi Hanazaki

IPC: H05K1/02 ,  H01B7/08 ,  H05K1/18 ,  H05K1/03 ,  H05K3/10 ,  H05K3/12

CPC classification number: H05K1/0263 ,  H01B7/0838 ,  H05K1/0265 ,  H05K1/028 ,  H05K1/0293 ,  H05K1/0393 ,  H05K1/181 ,  H05K3/101 ,  H05K3/102 ,  H05K3/125 ,  H05K3/1275 ,  H05K2201/0305 ,  H05K2201/09281 ,  H05K2201/09727 ,  H05K2201/09736 ,  H05K2201/10181 ,  H05K2203/107

Abstract: A flexible flat circuit includes a pair of insulation sheets, and a plurality of conductors that are held between and covered with the pair of insulation sheets in a state that the plurality of conductors are separated to each other. Among from the plurality of conductors, at least conductors with different current capacities are different in thickness to each other.

Abstract translation: 柔性扁平电路包括一对绝缘片，以及多个导体，其以多个导体彼此分离的状态保持在一对绝缘片之间并被其覆盖。 在多个导体中，至少具有不同电流容量的导体的厚度彼此不同。

公开(公告)号：US20160249822A1

公开(公告)日：2016-09-01

申请号：US15027314

申请日：2014-09-29

Applicant: KONINKLIJKE PHILIPS N.V.

Inventor： FRANCISCUS THEODORUS AGRICOLA ,  ALFONS WOUTER GROENLAND

IPC: A61B5/04 ,  H05K1/02 ,  A61N1/36

CPC classification number: A61B5/04001 ,  A61N1/0541 ,  A61N1/36036 ,  H05K1/028 ,  H05K1/0298 ,  H05K1/036 ,  H05K1/0393 ,  H05K3/0058 ,  H05K3/007 ,  H05K3/28 ,  H05K2201/051 ,  H05K2201/09281 ,  H05K2201/10151 ,  H05K2203/0384 ,  H05K2203/0769 ,  H05K2203/1322 ,  H05K2203/308 ,  Y10T428/1241 ,  Y10T428/12417

Abstract: A flexible conductive track arrangement has a pre-flexing condition in which the arrangement is generally planar. Conductive tracks are formed from a metal layer and they are covered above and below by insulator layers. The elongate conductive tracks are generally planar but locally corrugated perpendicularly to the general plane. This enables improved binding performance, for example to form tight windings using the conductive tracks.

Abstract translation: 柔性导电轨道装置具有预弯曲状态，其中该布置大体上是平面的。 导电轨道由金属层形成，并且它们被绝缘体层上下覆盖。 细长导电轨道通常是平面的，但是垂直于一般平面局部波纹。 这使得能够改善装订性能，例如使用导电轨迹形成紧密的绕组。

公开(公告)号：US09338882B2

公开(公告)日：2016-05-10

申请号：US14278330

申请日：2014-05-15

Applicant: Intel Corporation

Inventor： Kai Xiao ,  Raul Enriquez Shibayama ,  Gong Ouyang

IPC: H05K1/02 ,  H01P3/02 ,  H01P3/08 ,  H01P11/00 ,  B33Y10/00 ,  B33Y80/00

CPC classification number: H05K1/0245 ,  B33Y10/00 ,  B33Y80/00 ,  H01P3/02 ,  H01P3/08 ,  H01P11/003 ,  H05K2201/09281 ,  Y10T29/49156

Abstract: A broadside coupled differential design is described herein. The design may include a differential pair. Each trace of the differential pair includes a wide portion and a narrow portion. The wide portion of the first trace of the differential pair is to be aligned with a narrow portion of the second trace of the differential pair. Additionally, the wide portion of the second trace of the differential pair is to be aligned with a narrow portion of the first trace of the differential pair, such that the wide and narrow portions of the traces of the differential pair are staggered.

Abstract translation: 这里描述了宽边耦合差分设计。 该设计可以包括差分对。 差分对的每个迹线包括宽部分和窄部分。 差分对的第一迹线的宽部分将与差分对的第二迹线的窄部分对准。 此外，差分对的第二迹线的宽部分将与差分对的第一迹线的窄部分对齐，使得差分对的迹线的宽和窄部分交错。

公开(公告)号：US09282633B2

公开(公告)日：2016-03-08

申请号：US13519374

申请日：2012-06-11

Applicant: Hua Zheng ,  Cheng-hung Chen

Inventor： Hua Zheng ,  Cheng-hung Chen

IPC: H05K1/11 ,  H05K1/02

CPC classification number: H05K1/0269 ,  H05K1/0289 ,  H05K2201/09281 ,  H05K2201/09936

Abstract: The present invention provides a routing structure and display panel. The routing structure includes a plurality of routing, disposed separately. Each routing corresponds to a symbol, and the symbol is disposed on the routing to act as a part of the routing to conduct electricity. In this manner, the routing structure and display panel of the present invention allow expansion of routing width, effectively reduce RC constant and energy-consumption, and improve yield rate.

Abstract translation: 本发明提供一种路由结构和显示面板。 路由结构包括多个路由，分开设置。 每个路由对应于符号，并且该符号被布置在路由上以充当路由的一部分以进行电力。 以这种方式，本发明的路由结构和显示面板允许扩展路由宽度，有效降低RC常数和能量消耗，并提高成品率。

公开(公告)号：US20150129284A1

公开(公告)日：2015-05-14

申请号：US14076667

申请日：2013-11-11

Applicant: Seagate Technology LLC

Inventor： Prapan Aparimarn ,  Chaovalit Chiyatan ,  Piriyakorn Jirawattanakasem ,  Joompondej Bamrungwongtaree

IPC: H05K1/02 ,  H05K1/11

CPC classification number: H05K1/111 ,  G11B5/486 ,  H05K1/0296 ,  H05K1/056 ,  H05K1/11 ,  H05K3/3436 ,  H05K2201/09236 ,  H05K2201/09281 ,  H05K2201/09727 ,  Y02P70/611

Abstract: A printed circuit substrate may be configured with at least one internal lead designed and shaped to reduce solder bridging. The printed circuit substrate can have a plurality of internal leads that each has a continuously curvilinear boundary that defines an isolation channel. The isolation channel may be configured with a uniform distance that separates a first internal lead from an adjacent second internal lead.

Abstract translation: 印刷电路基板可以配置有至少一个设计和成形以减少焊料桥接的内部引线。 印刷电路基板可以具有多个内部引线，每个内部引线具有限定隔离通道的连续曲线边界。 隔离通道可以配置有将第一内部引线与相邻的第二内部引线分开的均匀距离。

公开(公告)号：US20150060395A1

公开(公告)日：2015-03-05

申请号：US14012240

申请日：2013-08-28

Applicant: RONALD STEVEN COK

Inventor： RONALD STEVEN COK

IPC: H05K3/12

CPC classification number: H05K1/0274 ,  H05K1/0298 ,  H05K1/097 ,  H05K3/0041 ,  H05K3/12 ,  H05K3/1258 ,  H05K3/1275 ,  H05K3/1283 ,  H05K3/1291 ,  H05K3/465 ,  H05K3/4685 ,  H05K2201/09209 ,  H05K2201/09281 ,  H05K2201/0979 ,  H05K2201/09845 ,  H05K2203/0108

Abstract: A method of making an imprinted micro-wire structure includes providing a substrate having an edge area and a central area separate from the edge area and providing a first stamp and a multi-level second stamp. A curable bottom layer and multi-layer are provided on the substrate. A bottom-layer micro-channel is imprinted in the bottom layer. A multi-layer micro-channel and a top-layer micro-channel are imprinted in the multi-layer. Micro-wires are formed in each micro-channel. The bottom-layer micro-wire extends from the central area into the edge area. The multi-layer micro-wire contacts the bottom-layer micro-wire in the edge area. The top-layer micro-wire is over the central area and is separate from the multi-layer micro-wire and the bottom-layer micro-channel. The bottom-layer micro-wire is electrically connected to the multi-layer micro-wire and is electrically isolated from the top-layer micro-wire.

Abstract translation: 制造压印微线结构的方法包括提供具有与边缘区域分离的边缘区域和中心区域的基板，并提供第一印模和多级第二印模。 在基板上设置有可固化的底层和多层。 底层微通道印在底层中。 多层微通道和顶层微通道印在多层中。 微线形成在每个微通道中。 底层微线从中心区域延伸到边缘区域。 多层微线接触边缘区域的底层微线。 顶层微线在中心区域之上，与多层微线和底层微通道分离。 底层微线电连接到多层微线，并与顶层微线电隔离。

公开(公告)号：US20150060394A1

公开(公告)日：2015-03-05

申请号：US14012216

申请日：2013-08-28

Applicant: RONALD STEVEN COK

Inventor： RONALD STEVEN COK

IPC: H05K3/12

CPC classification number: H05K1/0274 ,  H05K1/0298 ,  H05K1/097 ,  H05K3/0041 ,  H05K3/12 ,  H05K3/1258 ,  H05K3/1275 ,  H05K3/1283 ,  H05K3/1291 ,  H05K3/465 ,  H05K3/4685 ,  H05K2201/09209 ,  H05K2201/09281 ,  H05K2201/0979 ,  H05K2201/09845 ,  H05K2203/0108

Abstract: A method of making an imprinted micro-wire structure includes providing a substrate having an edge area and a central area separate from the edge area and providing first, second, and third different stamps. A curable bottom, connecting layer, and top layer are formed on the substrate. A bottom-layer micro-channel is imprinted in the bottom layer in the central area and the edge area, a connecting-layer micro-channel is imprinted in the connecting layer in the edge area over the bottom-layer micro-channel, an edge micro-channel is imprinted in the top layer in the edge area over the connecting-layer micro-channel, and top-layer micro-channels are imprinted in the top layer over the central area. Micro-wires are formed in each micro-channel. The bottom-layer micro-wire in the central area is electrically connected to the edge micro-wire in the edge area and is electrically isolated from the top-layer micro-wire.

Abstract translation: 制造压印微线结构的方法包括提供具有与边缘区域分离的边缘区域和中心区域的基板，并提供第一，第二和第三不同的邮票。 在基板上形成可固化的底部，连接层和顶层。 底层微通道印在中心区域和边缘区域的底层中，连接层微通道被压印在底层微通道上的边缘区域中的连接层中，边缘 微通道印在连接层微通道上的边缘区域的顶层中，顶层微通道印在中心区域的顶层中。 微线形成在每个微通道中。 中心区域的底层微线电连接到边缘区域中的边缘微线，并与顶层微线电隔离。

公开(公告)号：US20130201637A1

公开(公告)日：2013-08-08

申请号：US13574789

申请日：2011-01-31

Applicant: Margaretha Maria De Kok ,  Jeroen Van Den Brand ,  Gerardus Titus Van Heck

Inventor： Margaretha Maria De Kok ,  Jeroen Van Den Brand ,  Gerardus Titus Van Heck

IPC: H05K1/02 ,  H05K13/04 ,  H05B33/08

CPC classification number: H05K1/0277 ,  G09F9/00 ,  G09F19/22 ,  H01L27/3293 ,  H01L31/0392 ,  H01L31/042 ,  H01L51/5203 ,  H01L2251/5338 ,  H01L2251/5361 ,  H01R4/04 ,  H01R4/70 ,  H01R12/7076 ,  H05B33/0896 ,  H05B33/10 ,  H05K1/0283 ,  H05K1/038 ,  H05K1/147 ,  H05K1/189 ,  H05K3/321 ,  H05K3/325 ,  H05K3/365 ,  H05K13/04 ,  H05K2201/029 ,  H05K2201/0311 ,  H05K2201/046 ,  H05K2201/083 ,  H05K2201/09081 ,  H05K2201/09281 ,  H05K2201/10106 ,  H05K2201/10287 ,  H05K2201/10484 ,  Y02E10/50 ,  Y10T29/4913

Abstract: An assembly of a plurality of tiles (1) with a carrier (40), wherein the tiles (1) comprise a foil (20) with an electro-physical transducer (10) and electrical connectors (24, 28) to said transducer. The tiles are mechanically and electrically coupled to the carrier, and the tiles overlay according to a fish scale pattern.

Abstract translation: 具有载体（40）的多个瓦片（1）的组件，其中瓦片（1）包括具有电 - 物理换能器（10）的箔（20）和到所述换能器的电连接器（24,28）。 瓦片机械地和电耦合到载体上，并且瓦片根据鱼鳞图案覆盖。