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公开(公告)号:US20170318277A1
公开(公告)日:2017-11-02
申请号:US15652063
申请日:2017-07-17
Applicant: INTEL CORPORATION
Inventor: Wenhao Zhang , Yi-Jen Chiu , Lidong Xu , Yu Han , Zhipin Deng
IPC: H04N13/00 , H04N19/597 , H04N19/513
CPC classification number: H04N13/161 , H04N19/513 , H04N19/597
Abstract: Systems, apparatus, articles, and methods are described including operations for 3D video coding including depth based disparity vector calibration.
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公开(公告)号:US20160029040A1
公开(公告)日:2016-01-28
申请号:US14877650
申请日:2015-10-07
Applicant: INTEL CORPORATION
Inventor: Zhipin Deng , Yi-Jen Chiu , Lidong Xu , Wenhao Zhang , Yu Han , Xiaoxia Cai
IPC: H04N19/51 , H04N19/597 , H04N19/176
CPC classification number: H04N19/51 , H04N13/161 , H04N19/103 , H04N19/119 , H04N19/122 , H04N19/157 , H04N19/176 , H04N19/187 , H04N19/30 , H04N19/463 , H04N19/597 , H04N19/61 , H04N19/96
Abstract: A three-dimensional (3D) video codec encodes multiple views of a 3D video, each including texture and depth components. The encoders of the codec encode video blocks of their respective views based on a set of prediction parameters, such as quad-tree split flags, prediction modes, partition sizes, motion fields, inter directions, reference indices, luma intra modes, and chroma intra modes. The prediction parameters may be inherited across different views and different ones of the texture and depth components.
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公开(公告)号:US20140286408A1
公开(公告)日:2014-09-25
申请号:US13996574
申请日:2012-09-28
Applicant: INTEL CORPORATION
Inventor: Wenhao Zhang , Yi-Jen Chiu , Lidong Xu , Yu Han , Zhipin Deng , Xiaoxia Cai
IPC: H04N19/503
CPC classification number: H04N19/159 , H04N19/105 , H04N19/117 , H04N19/136 , H04N19/147 , H04N19/176 , H04N19/182 , H04N19/30 , H04N19/33 , H04N19/34 , H04N19/503 , H04N19/513 , H04N19/59 , H04N19/80
Abstract: Systems, devices and methods are described including performing scalable video coding using inter-layer pixel sample prediction. Inter-layer pixel sample prediction in an enhancement layer coding unit, prediction unit, or transform unit may use reconstructed pixel samples obtained from a base layer or from a lower enhancement layer. The pixel samples may be subjected to upsample filtering and/or refinement filtering. The upsample or refinement filter coefficients may be predetermined or may be adaptively determined.
Abstract translation: 描述了使用层间像素样本预测执行可缩放视频编码的系统,设备和方法。 增强层编码单元,预测单元或变换单元中的层间像素样本预测可以使用从基本层或较低增强层获得的重建像素样本。 可以对像素样本进行上采样滤波和/或细化滤波。 上采样或细化滤波器系数可以是预定的或可以被自适应地确定。
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公开(公告)号:US12206897B2
公开(公告)日:2025-01-21
申请号:US17898283
申请日:2022-08-29
Applicant: Intel Corporation
Inventor: Wenhao Zhang , Yi-Jen Chiu , Pieter Kapsenberg , Lidong Xu , Yu Han , Zhipin Apple Deng , Xiaoxia Cai
IPC: H04N19/60 , H04N19/122 , H04N19/91 , H04N19/96
Abstract: Systems, apparatus, articles, and methods are described including operations for size based transform unit context derivation. In an example encoder, first circuitry is to encode video input data into a bitstream according to a bitstream syntax, wherein the video input data includes one or more pictures, the one or more pictures are partitioned into one or more coding tree blocks, the one or more coding tree blocks are partitioned into slices including one or more coding tree blocks, the one or more coding tree blocks include one or more transform blocks according to a transform tree including a split_transform_flag indicative of the split of a given coding block into corresponding one or more transform blocks, the split_transform_flag is coded using CABAC, and a context index associated with the CABAC coding of the split_transform_flag is based on a value. Second circuitry of the encoder is to output the bitstream.
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公开(公告)号:US12147302B2
公开(公告)日:2024-11-19
申请号:US17095530
申请日:2020-11-11
Applicant: Intel Corporation
Inventor: Vasanth Ranganathan , Joydeep Ray , Abhishek R. Appu , Nikos Kaburlasos , Lidong Xu , Subramaniam Maiyuran , Altug Koker , Naveen Matam , James Holland , Brent Insko , Sanjeev Jahagirdar , Scott Janus , Durgaprasad Bilagi , Xinmin Tian
IPC: G06F11/10 , G06F12/0802 , G06T1/20 , G06T1/60
Abstract: Apparatuses including a graphics processing unit, graphics multiprocessor, or graphics processor having an error detection correction logic for cache memory or shared memory are disclosed. In one embodiment, a graphics multiprocessor includes cache or local memory for storing data and error detection correction circuitry integrated with or coupled to the cache or local memory. The error detection correction circuitry is configured to perform a tag read for data of the cache or local memory to check error detection correction information.
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公开(公告)号:US20230052483A1
公开(公告)日:2023-02-16
申请号:US17793341
申请日:2020-02-17
Applicant: Intel Corporation
Inventor: Xiaoxia Cai , Chen Wang , Huan Dou , Yi-Jen Chiu , Lidong Xu
Abstract: An apparatus for super resolution imaging includes a convolutional neural network (104) to receive a low resolution frame (102) and generate a high resolution illuminance component frame. The apparatus also includes a hardware scaler (106) to receive the low resolution frame (102) and generate a second high resolution chrominance component frame. The apparatus further includes a combiner (108) to combine the high resolution illuminance component frame and the high resolution chrominance component frame to generate a high resolution frame (110).
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公开(公告)号:US20220417559A1
公开(公告)日:2022-12-29
申请号:US17898283
申请日:2022-08-29
Applicant: Intel Corporation
Inventor: Wenhao Zhang , Yi-Jen Chiu , Pieter Kapsenberg , Lidong Xu , Yu Han , Zhipin Apple Deng , Xiaoxia Cai
IPC: H04N19/60 , H04N19/96 , H04N19/91 , H04N19/122
Abstract: Systems, apparatus, articles, and methods are described including operations for size based transform unit context derivation. In an example encoder, first circuitry is to encode video input data into a bitstream according to a bitstream syntax, wherein the video input data includes one or more pictures, the one or more pictures are partitioned into one or more coding tree blocks, the one or more coding tree blocks are partitioned into slices including one or more coding tree blocks, the one or more coding tree blocks include one or more transform blocks according to a transform tree including a split_transform_flag indicative of the split of a given coding block into corresponding one or more transform blocks, the split_transform_flag is coded using CABAC, and a context index associated with the CABAC coding of the split_transform_flag is based on a value. Second circuitry of the encoder is to output the bitstream.
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公开(公告)号:US11328496B2
公开(公告)日:2022-05-10
申请号:US16658803
申请日:2019-10-21
Applicant: Intel Corporation
Inventor: Ke Chen , Zhipin Deng , Xiaoxia Cai , Chen Wang , Ya-Ti Peng , Yi-Jen Chiu , Lidong Xu
Abstract: Systems, apparatus, articles, and methods are described below including operations for scalable real-time face beautification of video images.
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公开(公告)号:US20210314614A1
公开(公告)日:2021-10-07
申请号:US17121669
申请日:2020-12-14
Applicant: Intel Corporation
Inventor: Wenhao Zhang , Yi-Jen Chiu , Pieter Kapsenberg , Lidong Xu , Yu Han , Zhipin Apple Deng , Xiaoxia Cai
IPC: H04N19/60 , H04N19/96 , H04N19/91 , H04N19/122
Abstract: Systems, apparatus, articles, and methods are described including operations for size based transform unit context derivation.
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公开(公告)号:US20210150663A1
公开(公告)日:2021-05-20
申请号:US17095590
申请日:2020-11-11
Applicant: Intel Corporation
Inventor: Subramaniam Maiyuran , Durgaprasad Bilagi , Joydeep Ray , Scott Janus , Sanjeev Jahagirdar , Brent Insko , Lidong Xu , Abhishek R. Appu , James Holland , Vasanth Ranganathan , Nikos Kaburlasos , Altug Koker , Xinmin Tian , Guei-Yuan Lueh , Changliang Wang
IPC: G06T1/60 , G06T1/20 , G06N5/04 , G06F12/0802
Abstract: Embodiments described herein are generally directed to improvements relating to power, latency, bandwidth and/or performance issues relating to GPU processing/caching. According to one embodiment, a system includes a producer intellectual property (IP) (e.g., a media IP), a compute core (e.g., a GPU or an AI-specific core of the GPU), a streaming buffer logically interposed between the producer IP and the compute core. The producer IP is operable to consume data from memory and output results to the streaming buffer. The compute core is operable to perform AI inference processing based on data consumed from the streaming buffer and output AI inference processing results to the memory.
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