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公开(公告)号：US10319458B2
公开(公告)日：2019-06-11
申请号：US15457326
申请日：2017-03-13
Applicant: Intel Corporation
Inventor： Ashok Raj , Ron Gabor , Hisham Shafi , Mohan J. Kumar , Theodros Yigzaw
Abstract: Methods and apparatuses relating to a hardware memory test unit to check a section of a data storage device for a transient fault before the data is stored in and/or loaded from the section of the data storage device are described. In one embodiment, an integrated circuit includes a hardware processor to operate on data in a section of a data storage device, and a memory test unit to check the section of the data storage device for a transient fault before the data is stored in the section of the data storage device, wherein the transient fault is to cause a machine check exception if accessed by the hardware processor.
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公开(公告)号：US10296416B2
公开(公告)日：2019-05-21
申请号：US15201438
申请日：2016-07-02
Applicant: Intel Corporation
Inventor： Ashok Raj , Ron Gabor , Hisham Shafi , Sergiu Ghetie , Mohan J. Kumar , Theodros Yigzaw , Sarathy Jayakumar , Neeraj S. Upasani
Abstract: A processor of an aspect includes a decode unit to decode a read from memory instruction. The read from memory instruction is to indicate a source memory operand and a destination storage location. The processor also includes an execution unit coupled with the decode unit. The execution unit, in response to the read from memory instruction, is to read data from the source memory operand, store an indication of defective data in an architecturally visible storage location, when the data is defective, and complete execution of the read from memory instruction without causing an exceptional condition, when the data is defective. Other processors, methods, systems, and instructions are disclosed.
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公开(公告)号：US10162694B2
公开(公告)日：2018-12-25
申请号：US14977354
申请日：2015-12-21
Applicant: Intel Corporation
Inventor： Tomer Stark , Ron Gabor , Joseph Nuzman , Raanan Sade , Bryant E. Bigbee
Abstract: Methods and apparatuses relating to memory corruption detection are described. In one embodiment, a hardware processor includes an execution unit to execute an instruction to request access to a block of a memory through a pointer to the block of the memory, and a memory management unit to allow access to the block of the memory when a memory corruption detection value in the pointer is validated with a memory corruption detection value in the memory for the block, wherein a position of the memory corruption detection value in the pointer is selectable between a first location and a second, different location.
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公开(公告)号：US09904586B2
公开(公告)日：2018-02-27
申请号：US14925131
申请日：2015-10-28
Applicant: Intel Corporation
Inventor： Theodros Yigzaw , Mohan J. Kumar , Hisham Shafi , Ron Gabor , Ashok Raj
CPC classification number: G06F11/079 , G06F9/3004 , G06F9/30101 , G06F9/3016 , G06F11/0721 , G06F11/0784 , G06F11/0787 , G06F11/0793 , G06F12/00 , G06F12/0246
Abstract: In one embodiment, a processor includes a core having a fetch unit to fetch instructions, a decode unit to decode the instructions, and one or more execution units to execute the instructions. The core may further include: a first pair of block address range registers to store a start location and an end location of a block range within a non-volatile block storage coupled to the processor; and a block status storage to store an error indicator responsive to an occurrence of an error within the block range during a block operation. Other embodiments are described and claimed.
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公开(公告)号：US09690640B2
公开(公告)日：2017-06-27
申请号：US14038334
申请日：2013-09-26
Applicant: Intel Corporation
Inventor： Raanan Sade , Ron Gabor , Deep K. Buch , Theodros Yigzaw , Stanislav Shwartsman
CPC classification number: G06F11/073 , G06F11/0793 , G06F11/08
Abstract: Mechanisms for handling multiple data errors that occur simultaneously are provided. A processing device may determine whether multiple data errors occur in memory locations that are within a range of memory locations. If the multiple memory locations are within the range of memory locations, the processing device may continue with a recovery process. If one of the multiple memory locations is outside of the range of memory locations, the processing device may halt the recovery process.
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Patent Agency Ranking
36.发明授权Hardware apparatuses and methods to check data storage devices for transient faults 有权用于检查瞬态故障的数据存储设备的硬件设备和方法公开(公告)号：US09595349B2
公开(公告)日：2017-03-14
申请号：US14751113
申请日：2015-06-25
Applicant: Intel Corporation
Inventor： Ashok Raj , Ron Gabor , Hisham Shafi , Mohan J. Kumar , Theodros Yigzaw
CPC classification number: G11C29/38 , G11C13/0004 , G11C29/04 , G11C29/44 , G11C29/52 , G11C2029/0401
Abstract: Methods and apparatuses relating to a hardware memory test unit to check a section of a data storage device for a transient fault before the data is stored in and/or loaded from the section of the data storage device are described. In one embodiment, an integrated circuit includes a hardware processor to operate on data in a section of a data storage device, and a memory test unit to check the section of the data storage device for a transient fault before the data is stored in the section of the data storage device, wherein the transient fault is to cause a machine check exception if accessed by the hardware processor.
Abstract translation: 描述与硬件存储器测试单元相关的方法和装置，用于在将数据存储在数据存储设备的部分中和/或从数据存储设备的部分加载之前检查用于瞬态故障的数据存储设备的一部分。 在一个实施例中，集成电路包括用于对数据存储设备的一部分中的数据进行操作的硬件处理器，以及存储器测试单元，用于在将数据存储在该部分中之前检查数据存储设备中的瞬态故障的部分 的数据存储设备，其中如果由硬件处理器访问，则瞬态故障将导致机器检查异常。
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37.发明申请HARDWARE APPARATUSES AND METHODS TO CHECK DATA STORAGE DEVICES FOR TRANSIENT FAULTS 有权硬件设备和检查瞬时故障的数据存储设备的方法公开(公告)号：US20160379721A1
公开(公告)日：2016-12-29
申请号：US14751113
申请日：2015-06-25
Applicant: Intel Corporation
Inventor： Ashok Raj , Ron Gabor , Hisham Shafi , Mohan J. Kumar , Theodros Yigzaw
CPC classification number: G11C29/38 , G11C13/0004 , G11C29/04 , G11C29/44 , G11C29/52 , G11C2029/0401
Abstract: Methods and apparatuses relating to a hardware memory test unit to check a section of a data storage device for a transient fault before the data is stored in and/or loaded from the section of the data storage device are described. In one embodiment, an integrated circuit includes a hardware processor to operate on data in a section of a data storage device, and a memory test unit to check the section of the data storage device for a transient fault before the data is stored in the section of the data storage device, wherein the transient fault is to cause a machine check exception if accessed by the hardware processor.
Abstract translation: 描述与硬件存储器测试单元相关的方法和装置，用于在将数据存储在数据存储设备的部分中和/或从数据存储设备的部分加载之前检查用于瞬态故障的数据存储设备的一部分。 在一个实施例中，集成电路包括用于对数据存储设备的一部分中的数据进行操作的硬件处理器，以及存储器测试单元，用于在将数据存储在该部分中之前检查数据存储设备中的瞬态故障的部分 的数据存储设备，其中如果由硬件处理器访问，则瞬态故障将导致机器检查异常。
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公开(公告)号：US20160085287A1
公开(公告)日：2016-03-24
申请号：US14960887
申请日：2015-12-07
Applicant: Intel Corporation
Inventor： Nadav Bonen , Ron Gabor , Zeev Sperber , Vjekoslav Svilan , David N. Mackintosh , Jose A. Baiocchi Paredes , Naveen Kumar , Shantanu Gupta
CPC classification number: G06F1/3243 , G06F1/3287 , G06F9/30083 , G06F9/3869 , G06F9/3885 , Y02B70/123 , Y02B70/126 , Y02D10/152 , Y02D10/171
Abstract: In an embodiment, the present invention includes an execution unit to execute instructions of a first type, a local power gate circuit coupled to the execution unit to power gate the execution unit while a second execution unit is to execute instructions of a second type, and a controller coupled to the local power gate circuit to cause it to power gate the execution unit when an instruction stream does not include the first type of instructions. Other embodiments are described and claimed.
Abstract translation: 在一个实施例中，本发明包括执行单元，用于执行第一类型的指令，耦合到执行单元的本地电源门电路，以在第二执行单元执行第二类型的指令时对所述执行单元进行电源门控，以及 控制器，其耦合到所述本地电源门电路，以使得当指令流不包括所述第一类型的指令时，所述控制器对所述执行单元进行供电。 描述和要求保护其他实施例。
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公开(公告)号：US20230333994A1
公开(公告)日：2023-10-19
申请号：US18302664
申请日：2023-04-18
Applicant: Intel Corporation
Inventor： David M. Durham , Ron Gabor
CPC classification number: G06F12/1458 , G06F21/577 , G06F21/602 , G06F21/6218 , G06F2212/1052 , G06F2212/608 , G06F2221/034
Abstract: Embodiments are directed to memory protection with hidden inline metadata. An embodiment of an apparatus includes processor cores; a computer memory for the storage of data; and cache memory communicatively coupled with one or more of the processor cores, wherein one or more processor cores of the plurality of processor cores are to implant hidden inline metadata in one or more cachelines for the cache memory, the hidden inline metadata being hidden at a linear address level.
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公开(公告)号：US20230273846A1
公开(公告)日：2023-08-31
申请号：US18313905
申请日：2023-05-08
Applicant: Intel Corporation
Inventor： Tomer Stark , Ron Gabor , Joseph Nuzman , Raanan Sade , Bryant E. Bigbee
IPC: G06F11/07 , G06F12/00 , G06F9/38 , G06F12/109 , G06F21/60
CPC classification number: G06F11/0751 , G06F11/073 , G06F12/00 , G06F9/38 , G06F12/109 , G06F21/60 , G06F12/145
Abstract: Methods and apparatuses relating to memory corruption detection are described. In one embodiment, a hardware processor includes an execution unit to execute an instruction to request access to a block of a memory through a pointer to the block of the memory, and a memory management unit to allow access to the block of the memory when a memory corruption detection value in the pointer is validated with a memory corruption detection value in the memory for the block, wherein a position of the memory corruption detection value in the pointer is selectable between a first location and a second, different location.
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