公开(公告)号：US20230263076A1

公开(公告)日：2023-08-17

申请号：US18301439

申请日：2023-04-17

Applicant: Intel Corporation

Inventor： Jeanette M. Roberts ,  Ravi Pillarisetty ,  David J. Michalak ,  Zachary R. Yoscovits ,  James S. Clarke ,  Van H. Le

IPC: H10N60/10 ,  G06N10/00 ,  H10N60/12 ,  H10N60/80 ,  H10N60/01

CPC classification number: H10N60/128 ,  G06N10/00 ,  H10N60/12 ,  H10N60/805 ,  H10N60/0912

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a substrate and a quantum well stack disposed on the substrate. The quantum well stack may include a quantum well layer and a back gate, and the back gate may be disposed between the quantum well layer and the substrate.

公开(公告)号：US11721737B2

公开(公告)日：2023-08-08

申请号：US17401692

申请日：2021-08-13

Applicant: Intel Corporation

Inventor： Ravi Pillarisetty ,  Van H. Le ,  Jeanette M. Roberts ,  David J. Michalak ,  James S. Clarke ,  Zachary R. Yoscovits

IPC: H01L29/423 ,  H01L29/417 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78 ,  H01L29/06 ,  H01L29/778 ,  H01L29/165

CPC classification number: H01L29/42376 ,  H01L29/0649 ,  H01L29/41791 ,  H01L29/66431 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/66977 ,  H01L29/775 ,  H01L29/785 ,  H01L29/165 ,  H01L29/7781 ,  H01L29/7782

Abstract: Disclosed herein are quantum dot devices with trenched substrates, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a substrate having a trench disposed therein, wherein a bottom of the trench is provided by a first material, and a quantum well stack at least partially disposed in the trench. A material of the quantum well stack may be in contact with the bottom of the trench, and the material of the quantum well stack may be different from the first material.

公开(公告)号：US11569428B2

公开(公告)日：2023-01-31

申请号：US16347097

申请日：2016-12-27

Applicant: Intel Corporation

Inventor： Jeanette M. Roberts ,  Adel A. Elsherbini ,  Shawna Liff ,  Johanna M. Swan ,  Roman Caudillo ,  Zachary R. Yoscovits ,  Nicole K. Thomas ,  Ravi Pillarisetty ,  Hubert C. George ,  James S. Clarke

IPC: H01L27/32 ,  H01L39/04 ,  G06N10/00 ,  H01L39/02 ,  H01L39/22 ,  H01L39/24 ,  H01L25/00 ,  H01L23/48 ,  H01L23/00 ,  H01L27/18 ,  B82Y10/00 ,  H01L23/538 ,  H01L29/66

Abstract: One superconducting qubit device package disclosed herein includes a die having a first face and an opposing second face, and a package substrate having a first face and an opposing second face. The die includes a quantum device including a plurality of superconducting qubits and a plurality of resonators on the first face of the die, and a plurality of conductive pathways coupled between conductive contacts at the first face of the die and associated ones of the plurality of superconducting qubits or of the plurality of resonators. The second face of the package substrate also includes conductive contacts. The device package further includes first level interconnects disposed between the first face of the die and the second face of the package substrate, coupling the conductive contacts at the first face of the die with associated conductive contacts at the second face of the package substrate.

公开(公告)号：US11450798B2

公开(公告)日：2022-09-20

申请号：US16304809

申请日：2016-06-08

Applicant: Intel Corporation

Inventor： Jeanette M. Roberts ,  Ravi Pillarisetty ,  David J. Michalak ,  Zachary R. Yoscovits ,  James S. Clarke

IPC: H01L39/22 ,  G06N10/00 ,  H01L39/02 ,  H01L39/12 ,  H01L39/24

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a gate disposed on a quantum well stack; an insulating material disposed on the gate; and a conductive via extending through the insulating material and in conductive contact with the gate.

公开(公告)号：US11417765B2

公开(公告)日：2022-08-16

申请号：US16017942

申请日：2018-06-25

Applicant: Intel Corporation

Inventor： Nicole K. Thomas ,  Ravi Pillarisetty ,  Kanwaljit Singh ,  Hubert C. George ,  David J. Michalak ,  Lester Lampert ,  Zachary R. Yoscovits ,  Roman Caudillo ,  Jeanette M. Roberts ,  James S. Clarke

IPC: H01L29/06 ,  H01L29/778 ,  H01L29/78 ,  H01L23/522 ,  H01L29/66 ,  H01L29/76 ,  H01L29/12 ,  H01L29/40 ,  H01L29/423 ,  B82Y30/00 ,  B82Y10/00

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack; a first gate above the quantum well stack, wherein the first gate includes a first gate metal and a first gate dielectric layer; and a second gate above the quantum well stack, wherein the second gate includes a second gate metal and a second gate dielectric layer, and the second gate dielectric layer extends over the first gate.

公开(公告)号：US20220216305A1

公开(公告)日：2022-07-07

申请号：US17704906

申请日：2022-03-25

Applicant: Intel Corporation

Inventor： Nicole K. Thomas ,  Ravi Pillarisetty ,  Kanwaljit Singh ,  Hubert C. George ,  David J. Michalak ,  Lester Lampert ,  Zachary R. Yoscovits ,  Roman Caudillo ,  Jeanette M. Roberts ,  James S. Clarke

IPC: H01L29/12 ,  H01L29/78 ,  H01L29/10 ,  H01L29/423 ,  H01L29/66 ,  H01L21/28 ,  H01L23/46 ,  H01L29/43 ,  G06N10/00 ,  B82Y10/00 ,  H01L29/76 ,  H01L29/40

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack; a first gate above the quantum well stack, wherein the first gate includes a first gate metal and a first gate dielectric; and a second gate above the quantum well stack, wherein the second gate includes a second gate metal and a second gate dielectric, and the first gate is at least partially between a portion of the second gate and the quantum well stack.

公开(公告)号：US11355623B2

公开(公告)日：2022-06-07

申请号：US15924407

申请日：2018-03-19

Applicant: Intel Corporation

Inventor： Lester Lampert ,  James S. Clarke ,  Jeanette M. Roberts ,  Ravi Pillarisetty ,  David J. Michalak ,  Kanwaljit Singh ,  Roman Caudillo ,  Hubert C. George ,  Zachary R. Yoscovits ,  Nicole K. Thomas

IPC: H01L29/66 ,  H01L29/82 ,  H01L29/49 ,  H01L29/40 ,  G06N10/00 ,  H01L29/423 ,  H01L21/266 ,  B82Y10/00 ,  H01L29/76 ,  H01L21/265 ,  B82Y30/00 ,  B82Y40/00

Abstract: Embodiments of the present disclosure describe a method of fabricating spin qubit device assemblies that utilize dopant-based spin qubits, i.e. spin qubit devices which operate by including a donor or an acceptor dopant atom in a semiconductor host layer. The method includes, first, providing a pair of gate electrodes over a semiconductor host layer, and then providing a window structure between the first and second gate electrodes, the window structure being a continuous solid material extending between the first and second electrodes and covering the semiconductor host layer except for an opening through which a dopant atom is to be implanted in the semiconductor host layer. By using a defined gate-first process, the method may address the scalability challenges and create a deterministic path for fabricating dopant-based spin qubits in desired locations, promoting wafer-scale integration of dopant-based spin qubit devices for use in quantum computing devices.

公开(公告)号：US11335778B2

公开(公告)日：2022-05-17

申请号：US16018751

申请日：2018-06-26

Applicant: Intel Corporation

Inventor： Nicole K. Thomas ,  Ravi Pillarisetty ,  Kanwaljit Singh ,  Hubert C. George ,  David J. Michalak ,  Lester Lampert ,  Zachary R. Yoscovits ,  Roman Caudillo ,  Jeanette M. Roberts ,  James S. Clarke

IPC: H01L29/12 ,  H01L29/78 ,  H01L29/10 ,  H01L29/423 ,  H01L29/66 ,  H01L21/28 ,  H01L23/46 ,  H01L29/43 ,  G06N10/00 ,  B82Y10/00 ,  H01L29/76 ,  H01L29/40 ,  H01L21/306 ,  H01L21/02 ,  H01L21/324 ,  H01L21/311 ,  H01L29/778 ,  H01L29/82

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack; a first gate above the quantum well stack, wherein the first gate includes a first gate metal and a first gate dielectric; and a second gate above the quantum well stack, wherein the second gate includes a second gate metal and a second gate dielectric, and the first gate is at least partially between a portion of the second gate and the quantum well stack.

公开(公告)号：US20220013658A1

公开(公告)日：2022-01-13

申请号：US17472015

申请日：2021-09-10

Applicant: Intel Corporation

Inventor： Ravi Pillarisetty ,  Van H. Le ,  Nicole K. Thomas ,  Hubert C. George ,  Jeanette M. Roberts ,  Payam Amin ,  Zachary R. Yoscovits ,  Roman Caudillo ,  James S. Clarke ,  Roza Kotlyar ,  Kanwaljit Singh

IPC: H01L29/66 ,  G06N10/00 ,  H01L21/8234 ,  H01L27/088 ,  H01L27/12 ,  H01L29/15 ,  H01L29/78 ,  H01L29/82

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include a (111) silicon substrate, a (111) germanium quantum well layer above the substrate, and a plurality of gates above the quantum well layer. In some embodiments, a quantum dot device may include a silicon substrate, an insulating material above the silicon substrate, a quantum well layer above the insulating material, and a plurality of gates above the quantum well layer.

公开(公告)号：US11107891B2

公开(公告)日：2021-08-31

申请号：US16650299

申请日：2017-12-23

Applicant: Intel Corporation

Inventor： Ravi Pillarisetty ,  Hubert C. George ,  Nicole K. Thomas ,  Jeanette M. Roberts ,  Roman Caudillo ,  Zachary R. Yoscovits ,  Kanwaljit Singh ,  Roza Kotlyar ,  Patrick H. Keys ,  James S. Clarke

IPC: H01L29/15 ,  G06N10/00 ,  B82Y10/00

Abstract: Quantum dot devices, and related systems and methods, are disclosed herein. In some embodiments, a quantum dot device may include a quantum well stack; a plurality of first gates above the quantum well stack; and a plurality of second gates above the quantum well stack; wherein the plurality of first gates are arranged in electrically continuous first rows and the plurality of second gates are arranged in electrically continuous second rows parallel to the first rows. Quantum dot devices according to various embodiments of the present disclosure are based on arranging first and second gates in hexagonal/honeycomb arrays.