公开(公告)号：US11183564B2

公开(公告)日：2021-11-23

申请号：US16015087

申请日：2018-06-21

Applicant: Intel Corporation

Inventor： Nicole K. Thomas ,  Ravi Pillarisetty ,  Payam Amin ,  Roza Kotlyar ,  Patrick H. Keys ,  Hubert C. George ,  Kanwaljit Singh ,  James S. Clarke ,  David J. Michalak ,  Lester Lampert ,  Zachary R. Yoscovits ,  Roman Caudillo ,  Jeanette M. Roberts

IPC: H01L29/12 ,  H01L29/66 ,  H01L29/76 ,  H01L29/423 ,  H01L29/165 ,  H01L27/18 ,  H01L21/8234 ,  H01L29/10 ,  G06N10/00 ,  H01L39/14 ,  H01L29/06 ,  B82Y10/00 ,  H01L29/82 ,  H01L29/40 ,  H01L21/321 ,  H01L21/02 ,  H01L29/778 ,  H01L29/43

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack including a quantum well layer and a barrier layer; a first gate metal above the quantum well stack, wherein the barrier layer is between the first gate metal and the quantum well layer; and a second gate metal above the quantum well stack, wherein the barrier layer is between the second gate metal and the quantum well layer, and a material structure of the second gate metal is different from a material structure of the first gate metal.

公开(公告)号：US20190043951A1

公开(公告)日：2019-02-07

申请号：US16015087

申请日：2018-06-21

Applicant: Intel Corporation

Inventor： Nicole K. Thomas ,  Ravi Pillarisetty ,  Payam Amin ,  Roza Kotlyar ,  Patrick H. Keys ,  Hubert C. George ,  Kanwaljit Singh ,  James S. Clarke ,  David J. Michalak ,  Lester Lampert ,  Zachary R. Yoscovits ,  Roman Caudillo ,  Jeanette M. Roberts

IPC: H01L29/12 ,  H01L29/10 ,  H01L29/423 ,  H01L29/165 ,  H01L21/02 ,  H01L29/66 ,  H01L29/778 ,  G06N99/00

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack including a quantum well layer and a barrier layer; a first gate metal above the quantum well stack, wherein the barrier layer is between the first gate metal and the quantum well layer; and a second gate metal above the quantum well stack, wherein the barrier layer is between the second gate metal and the quantum well layer, and a material structure of the second gate metal is different from a material structure of the first gate metal.

公开(公告)号：US12230687B2

公开(公告)日：2025-02-18

申请号：US17117337

申请日：2020-12-10

Applicant: Intel Corporation

Inventor： Roza Kotlyar ,  Stephanie A. Bojarski ,  Hubert C. George ,  Payam Amin ,  Patrick H. Keys ,  Ravi Pillarisetty ,  Roman Caudillo ,  Florian Luethi ,  James S. Clarke

IPC: H01L29/49 ,  B82Y10/00 ,  B82Y30/00 ,  G06N10/00 ,  H01L29/06 ,  H01L29/15 ,  H01L29/423

Abstract: Disclosed herein are lateral gate material arrangements for quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack; and a gate above the quantum well stack, wherein the gate includes a gate electrode, the gate electrode includes a first material proximate to side faces of the gate and a second material proximate to a center of the gate, and the first material has a different material composition than the second material.

公开(公告)号：US20200321436A1

公开(公告)日：2020-10-08

申请号：US16650299

申请日：2017-12-23

Applicant: Intel Corporation

Inventor： Ravi Pillarisetty ,  Hubert C. George ,  Nicole K. Thomas ,  Jeanette M. Roberts ,  Roman Caudillo ,  Zachary R. Yoscovits ,  Kanwaljit Singh ,  Roza Kotlyar ,  Patrick H. Keys ,  James S. Clarke

IPC: H01L29/15 ,  G06N10/00

Abstract: Quantum dot devices, and related systems and methods, are disclosed herein. In some embodiments, a quantum dot device may include a quantum well stack; a plurality of first gates above the quantum well stack; and a plurality of second gates above the quantum well stack; wherein the plurality of first gates are arranged in electrically continuous first rows and the plurality of second gates are arranged in electrically continuous second rows parallel to the first rows. Quantum dot devices according to various embodiments of the present disclosure are based on arranging first and second gates in hexagonal/honeycomb arrays.

公开(公告)号：US10790281B2

公开(公告)日：2020-09-29

申请号：US15773325

申请日：2015-12-03

Applicant: Intel Corporation

Inventor： Rishabh Mehandru ,  Roza Kotlyar ,  Stephen M. Cea ,  Patrick H. Keys

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/10 ,  H01L27/06 ,  H01L29/78 ,  H01L21/822 ,  H01L27/12 ,  H01L21/84 ,  H01L29/66

Abstract: Disclosed herein are stacked channel structures for metal oxide semiconductor field effect transistors (MOSFETs) and related circuit elements, computing devices, and methods. For example, a stacked channel structure may include: a semiconductor substrate having a substrate lattice constant; a fin extending away from the semiconductor substrate, the fin having an upper region and a lower region; a first transistor in the lower region, wherein the first transistor has a first channel, the first channel has a first lattice constant, and the first lattice constant is different from the substrate lattice constant; and a second transistor in the upper region, wherein the second transistor has a second channel, the second channel has a second lattice constant, and the second lattice constant is different from the substrate lattice constant.

公开(公告)号：US12100623B2

公开(公告)日：2024-09-24

申请号：US17848191

申请日：2022-06-23

Applicant: Intel Corporation

Inventor： Aaron Lilak ,  Sean Ma ,  Justin R. Weber ,  Rishabh Mehandru ,  Stephen M. Cea ,  Patrick Morrow ,  Patrick H. Keys

IPC: H01L21/822 ,  H01L21/306 ,  H01L21/311 ,  H01L21/8238 ,  H01L21/8258 ,  H01L27/092 ,  H01L29/417 ,  H01L29/66

CPC classification number: H01L21/8221 ,  H01L21/30604 ,  H01L21/31111 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823878 ,  H01L21/8258 ,  H01L27/0924 ,  H01L29/41791 ,  H01L29/66545

Abstract: Stacked finFET structures including a fin having at least a first layer of semiconductor material stacked over or under a second layer of semiconductor material. The first and second layers may include a Group IV semiconductor material layer and a Group III-V semiconductor material layer, for example. A stacked finFET may include an N-type finFET stacked over or under a P-type finFET, the two finFETs may have channel portions within the different semiconductor material layers. Channel portions of the first and second layers of semiconductor material may be coupled to separate gate electrodes that are vertically aligned. Channel portions of the first and second layers of semiconductor material may be vertically separated by subfin portions of the first and second layers. Different layers of dielectric material adjacent to the subfin portions may improve electrical isolation between the channel portions, for example as a source of fixed charge or impurity dopants.

公开(公告)号：US20220336284A1

公开(公告)日：2022-10-20

申请号：US17848191

申请日：2022-06-23

Applicant: Intel Corporation

Inventor： Aaron Lilak ,  Sean Ma ,  Justin R. Weber ,  Rishabh Mehandru ,  Stephen M. Cea ,  Patrick Morrow ,  Patrick H. Keys

IPC: H01L21/822 ,  H01L21/306 ,  H01L21/311 ,  H01L21/8238 ,  H01L21/8258 ,  H01L27/092 ,  H01L29/417 ,  H01L29/66

Abstract: Stacked finFET structures including a fin having at least a first layer of semiconductor material stacked over or under a second layer of semiconductor material. The first and second layers may include a Group IV semiconductor material layer and a Group III-V semiconductor material layer, for example. A stacked finFET may include an N-type finFET stacked over or under a P-type finFET, the two finFETs may have channel portions within the different semiconductor material layers. Channel portions of the first and second layers of semiconductor material may be coupled to separate gate electrodes that are vertically aligned. Channel portions of the first and second layers of semiconductor material may be vertically separated by subfin portions of the first and second layers. Different layers of dielectric material adjacent to the subfin portions may improve electrical isolation between the channel portions, for example as a source of fixed charge or impurity dopants.

公开(公告)号：US10978590B2

公开(公告)日：2021-04-13

申请号：US16327728

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Aaron D. Lilak ,  Rishabh Mehandru ,  Patrick Morrow ,  Patrick H. Keys

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/78 ,  H01L29/66 ,  H01L21/762 ,  H01L21/302 ,  H01L21/768 ,  H01L21/304

Abstract: Methods and apparatus to remove epitaxial defects in semiconductors are disclosed. A disclosed example multilayered die structure includes a fin having a first material, where the fin is epitaxially grown from a first substrate layer having a second material, and where a defect portion of the fin is etched or polished. The disclosed example multilayered die structure also includes a second substrate layer having an opening through which the fin extends.

公开(公告)号：US10896907B2

公开(公告)日：2021-01-19

申请号：US16318361

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Patrick H. Keys ,  Hei Kam ,  Rishabh Mehandru ,  Aaron A. Budrevich

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/78 ,  H01L29/10 ,  H01L29/167 ,  H01L29/43 ,  H01L29/49

Abstract: A transistor including a gate stack and source and drain on opposing sides of the gate stack; and a first material and a second material on the substrate, the first material disposed between the substrate and the second material and the channel of the transistor is defined in the second material between the source and drain, wherein the first material and the second material each include an implant and the implant includes a greater solubility in the first material than in the second material. A method for forming an integrated circuit structure including forming a first material on a substrate; forming a second material on the first material; introducing an implant into the second material, wherein the implant includes a greater solubility in the first material than in the second material; annealing the substrate; and forming a transistor on the substrate, the transistor including a channel including the second material.

公开(公告)号：US20200235013A1

公开(公告)日：2020-07-23

申请号：US16635108

申请日：2017-08-24

Applicant: Intel Corporation

Inventor： Aaron Lilak ,  Sean Ma ,  Justin R. Weber ,  Rishabh Mehandru ,  Stephen M. Cea ,  Patrick Morrow ,  Patrick H. Keys

IPC: H01L21/822 ,  H01L29/417 ,  H01L21/8258 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/306 ,  H01L21/311

Abstract: Stacked finFET structures including a fin having at least a first layer of semiconductor material stacked over or under a second layer of semiconductor material. The first and second layers may include a Group IV semiconductor material layer and a Group III-V semiconductor material layer, for example. A stacked finFET may include an N-type finFET stacked over or under a P-type finFET, the two finFETs may have channel portions within the different semiconductor material layers. Channel portions of the first and second layers of semiconductor material may be coupled to separate gate electrodes that are vertically aligned. Channel portions of the first and second layers of semiconductor material may be vertically separated by subfin portions of the first and second layers. Different layers of dielectric material adjacent to the subfin portions may improve electrical isolation between the channel portions, for example as a source of fixed charge or impurity dopants.