公开(公告)号：US09865387B2

公开(公告)日：2018-01-09

申请号：US14956859

申请日：2015-12-02

Applicant: Intel IP Corporation

Inventor： Sven Albers ,  Klaus Reingruber ,  Andreas Wolter

IPC: H01F5/00 ,  H01F27/06 ,  H01F27/28 ,  H01F27/24

CPC classification number: H01F27/2804 ,  H01F27/06 ,  H01F27/24 ,  H01F2027/065 ,  H01F2027/2809

Abstract: An electronic package that includes a substrate; a first electronic component mounted on one side of the substrate; a second electronic component mounted on an opposing side of the substrate; a core mounted to the substrate, wherein the core extends through the substrate; a first wire electrically attached to at least one of the first electronic component and the substrate, wherein the first wire is wrapped around the core to form a first coil on the one side of the substrate; and a second wire electrically attached to at least one of the second electronic component and the substrate, wherein the second wire is wrapped around the core to form a second coil on the opposing side of the substrate.

公开(公告)号：US09653324B2

公开(公告)日：2017-05-16

申请号：US15182434

申请日：2016-06-14

Applicant: INTEL IP CORPORATION

Inventor： Sven Albers ,  Sonja Koller ,  Thorsten Meyer ,  Georg Seidemann ,  Christian Geissler ,  Andreas Wolter

IPC: H01L21/44 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L21/78

CPC classification number: H01L21/56 ,  H01L21/568 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/562 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/3511 ,  H01L2924/00

Abstract: Embodiments of the present disclosure are directed towards an integrated circuit (IC) package including a die having a first side and a second side disposed opposite to the first side. The IC package may further include an encapsulation material encapsulating at least a portion of the die and having a first surface that is adjacent to the first side of the die and a second surface disposed opposite to the first surface. In embodiments, the second surface may be shaped such that one or more cross-section areas of the IC package are thinner than one or more other cross-section areas of the IC package. Other embodiments may be described and/or claimed.

公开(公告)号：US20160293453A1

公开(公告)日：2016-10-06

申请号：US15182434

申请日：2016-06-14

Applicant: INTEL IP CORPORATION

Inventor： Sven Albers ,  Sonja Koller ,  Thorsten Meyer ,  Georg Seidemann ,  Christian Geissler ,  Andreas Wolter

IPC: H01L21/56 ,  H01L23/00 ,  H01L21/78 ,  H01L23/31

CPC classification number: H01L21/56 ,  H01L21/568 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/562 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/3511 ,  H01L2924/00

Abstract: Embodiments of the present disclosure are directed towards an integrated circuit (IC) package including a die having a first side and a second side disposed opposite to the first side. The IC package may further include an encapsulation material encapsulating at least a portion of the die and having a first surface that is adjacent to the first side of the die and a second surface disposed opposite to the first surface. In embodiments, the second surface may be shaped such that one or more cross-section areas of the IC package are thinner than one or more other cross-section areas of the IC package. Other embodiments may be described and/or claimed.

公开(公告)号：US10784033B2

公开(公告)日：2020-09-22

申请号：US16367200

申请日：2019-03-27

Applicant: Intel IP Corporation

Inventor： Andreas Wolter ,  Thorsten Meyer ,  Gerhard Knoblinger

IPC: H01L23/64 ,  H01F17/00 ,  H01F41/04 ,  H01L23/522 ,  H01L23/00 ,  H01F27/28

Abstract: Embodiments of the invention include a microelectronic device and methods of forming a microelectronic device. In an embodiment the microelectronic device includes a semiconductor die and an inductor that is electrically coupled to the semiconductor die. The inductor may include one or more conductive coils that extend away from a surface of the semiconductor die. In an embodiment each conductive coils may include a plurality of traces. For example, a first trace and a third trace may be formed over a first dielectric layer and a second trace may be formed over a second dielectric layer and over a core. A first via through the second dielectric layer may couple the first trace to the second trace, and a second via through the second dielectric layer may couple the second trace to the third trace.

公开(公告)号：US10727197B2

公开(公告)日：2020-07-28

申请号：US15464920

申请日：2017-03-21

Applicant: Intel IP Corporation

Inventor： Bernd Waidhas ,  Georg Seidemann ,  Andreas Wolter ,  Thomas Wagner ,  Stephan Stoeckl ,  Laurent Millou

IPC: H01L25/065 ,  H01L23/538 ,  H01L23/498 ,  H01L23/00 ,  H01L21/56 ,  H01L25/00 ,  H01L21/683

Abstract: An embedded-bridge substrate connector apparatus includes a patterned reference layer to which a first module and a subsequent module are aligned and the two modules are mated at the patterned reference layer. At least one module includes a silicon bridge connector that bridges to two devices, through the patterned reference layer, to the mated module.

公开(公告)号：US20200020629A1

公开(公告)日：2020-01-16

申请号：US16469113

申请日：2016-12-30

Applicant: Intel IP Corporation

Inventor： Thomas Wagner ,  Andreas Wolter ,  Georg Seidemann

IPC: H01L23/522 ,  H01L23/00 ,  H01L23/538

Abstract: A microelectronic package includes at least two semiconductor die, one die stacked over at least partially another. At a least the upper die is oriented with its active surface facing in the direction of a redistribution structure, and one or more wires are coupled to extend from contacts on that active surface into conductive structures in the redistribution structure.

公开(公告)号：US10522485B2

公开(公告)日：2019-12-31

申请号：US15776474

申请日：2015-12-21

Applicant: Intel IP Corporation

Inventor： Christian Geissler ,  Sven Albers ,  Georg Seidemann ,  Andreas Wolter ,  Klaus Reingruber ,  Thomas Wagner ,  Marc Dittes

IPC: H01L23/52 ,  H01L23/00 ,  H01L21/768 ,  H01L23/525 ,  H01L23/532

Abstract: An electrical device includes a redistribution layer structure, an inter-diffusing material contact structure and a vertical electrically conductive structure located between the redistribution layer structure and the inter-diffusing material contact structure. The vertical electrically conductive structure includes a diffusion barrier structure located adjacently to the inter-diffusing material contact structure. Further, the diffusion barrier structure and the redistribution layer structure comprise different lateral dimensions.

公开(公告)号：US20190333886A1

公开(公告)日：2019-10-31

申请号：US16505307

申请日：2019-07-08

Applicant: Intel IP Corporation

Inventor： Klaus Reingruber ,  Andreas Wolter ,  Georg Seidemann ,  Thomas Wagner ,  Bernd Waidhas

IPC: H01L23/00 ,  H01L25/00 ,  H01L23/31 ,  H01L25/11

Abstract: A microelectronic package with two semiconductor die coupled on opposite sides of a redistribution layer 108, and at least partially overlapping with one another. At least a first of the semiconductor die includes two sets of contacts, the first group of contacts arranged at a lesser pitch relative to one another than are a second group of contacts. The first group of contacts at the larger pitch are placed to engage contacts in a redistribution layer 108. The second group of contacts at the lesser pitch are placed to engage respective contacts at the same pitch on the second semiconductor die.

公开(公告)号：US20190221349A1

公开(公告)日：2019-07-18

申请号：US16367200

申请日：2019-03-27

Applicant: Intel IP Corporation

Inventor： Andreas Wolter ,  Thorsten Meyer ,  Gerhard Knoblinger

IPC: H01F17/00 ,  H01L23/64 ,  H01F41/04

Abstract: Embodiments of the invention include a microelectronic device and methods of forming a microelectronic device. In an embodiment the microelectronic device includes a semiconductor die and an inductor that is electrically coupled to the semiconductor die. The inductor may include one or more conductive coils that extend away from a surface of the semiconductor die. In an embodiment each conductive coils may include a plurality of traces. For example, a first trace and a third trace may be formed over a first dielectric layer and a second trace may be formed over a second dielectric layer and over a core. A first via through the second dielectric layer may couple the first trace to the second trace, and a second via through the second dielectric layer may couple the second trace to the third trace.

公开(公告)号：US20190103333A1

公开(公告)日：2019-04-04

申请号：US15719653

申请日：2017-09-29

Applicant: Intel IP Corporation

Inventor： Reinhard Mahnkopf ,  Andreas Wolter ,  Sonja Koller

IPC: H01L23/367 ,  H01L23/373 ,  H01L23/498 ,  H01L27/02 ,  H01L27/12 ,  H01L21/48 ,  H01L21/762

Abstract: A semiconductor device includes a plurality of circuit regions formed at a circuit semiconductor layer of a semiconductor die. The semiconductor device includes an etch stop layer of the semiconductor die arranged between the circuit semiconductor layer of the semiconductor die and a handling layer of the semiconductor die. The semiconductor device includes one or more trench structures extending through the handling layer of the semiconductor die. The one or more trench structures extends to at least the etch stop layer and to at most the circuit semiconductor layer of the semiconductor die.