公开(公告)号：US10431545B2

公开(公告)日：2019-10-01

申请号：US15637641

申请日：2017-06-29

Applicant: Intel IP Corporation

Inventor： Georg Seidemann ,  Bernd Waidhas ,  Thomas Wagner ,  Andreas Wolter ,  Laurent Millou

IPC: H01L23/538 ,  H01L23/498 ,  H01L25/065 ,  G11C16/18

Abstract: A multi-chip module includes two silicon bridge interconnects and three components that are tied together by the bridges with one of the components in the center. At least one of the silicon bridge interconnects is bent to create a non-planar chip-module form factor. Cross-connected multi-chip silicon bent-bridge interconnect modules include the two silicon bridges contacting the center component at right angles to each other, plus a fourth component and a third silicon bridge interconnect contacting the fourth component and any one of the original three components.

公开(公告)号：US20190295857A1

公开(公告)日：2019-09-26

申请号：US15935128

申请日：2018-03-26

Applicant: Intel IP Corporation

Inventor： Sonja Koller ,  Georg Seidemann ,  Bernd Waidhas

IPC: H01L21/48 ,  H01L23/498

Abstract: A method for forming a carrier substrate for a semiconductor device, the method includes providing a substrate layer including conductive particles embedded in an electrically insulating material and localized heating of the substrate layer along a desired trace by a laser to form a conductive trace of merged particles along the desired trace.

公开(公告)号：US20190267312A1

公开(公告)日：2019-08-29

申请号：US16349359

申请日：2016-12-29

Applicant: Intel IP Corporation

Inventor： Sonja Koller ,  Georgg Seidemann ,  Reinhard Mahnkopf ,  Bernd Waidhas

IPC: H01L23/495 ,  H01L23/498 ,  H01L23/538 ,  H01L23/367 ,  H01L23/373

Abstract: A system-in-package apparatus includes a square wave lead frame that provides a recess for a first semiconductive device as well as a feature for a second device. The system-in-package apparatus includes a printed wiling board that is wrapped onto the lead frame after a manner to enclose the first semiconductive device into the recess.

公开(公告)号：US20190206800A1

公开(公告)日：2019-07-04

申请号：US15858103

申请日：2017-12-29

Applicant: Intel IP Corporation

Inventor： Lizabeth Keser ,  Thomas Ort ,  Thomas Wagner ,  Bernd Waidhas

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L23/5389 ,  H01L21/481 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49833 ,  H01L23/5383 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/16227 ,  H01L2224/224 ,  H01L2924/15172 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/18161

Abstract: An electronic device may include a semiconductor die. The electronic device may include a first routing layer. The first routing layer may be coupled to the semiconductor die. A first plurality of routing traces may be in electrical communication with the semiconductor die. The first plurality of routing traces may be positioned within a first routing footprint. The first routing footprint may have a width greater than a width of the semiconductor die.A second routing layer may be coupled to the first routing layer. A second plurality of routing traces may be in electrical communication with the first plurality of routing traces. The second plurality of routing traces may be positioned within a second routing footprint. The second routing footprint may have a width greater than the width of the first routing footprint.

公开(公告)号：US20190198478A1

公开(公告)日：2019-06-27

申请号：US15853173

申请日：2017-12-22

Applicant: Intel IP Corporation

Inventor： Lizabeth Keser ,  Thomas Ort ,  Thomas Wagner ,  Bernd Waidhas

IPC: H01L23/00 ,  H01L23/538 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78 ,  H01L21/66

Abstract: A semiconductor device and method is disclosed. Devices shown include a die coupled to an integrated routing layer, wherein the integrated routing layer includes a first width that is wider than the die. Devices shown further included a molded routing layer coupled to the integrated routing layer.

公开(公告)号：US10263106B2

公开(公告)日：2019-04-16

申请号：US15476270

申请日：2017-03-31

Applicant: Intel IP Corporation

Inventor： Bernd Waidhas ,  Sonja Koller ,  Georg Seidemann

IPC: H01L23/52 ,  H01L21/82 ,  H01L29/78 ,  H01L23/00 ,  H01L29/66 ,  H01L23/498 ,  H01L23/50

Abstract: A power mesh-on-die apparatus includes a solder trace that enhances current flow for a power source trace between adjacent power bumps. The solder trace is also applied between power drain bumps on a power drain trace.

公开(公告)号：US20170170111A1

公开(公告)日：2017-06-15

申请号：US14970355

申请日：2015-12-15

Applicant: Intel IP Corporation

Inventor： Klaus Jürgen REINGRUBER ,  Sven Albers ,  Christian Georg Geissler ,  Georg Seidemann ,  Bernd Waidhas ,  Thomas Wagner ,  Marc Dittes

IPC: H01L23/528 ,  H01L23/00 ,  H05K1/11 ,  C25D5/54 ,  C25D7/12 ,  C25D5/02 ,  C25D5/10 ,  C25D5/48 ,  H01L23/522 ,  H05K1/02

CPC classification number: H01L23/528 ,  C25D5/022 ,  C25D5/10 ,  C25D5/48 ,  C25D5/54 ,  C25D7/123 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/5226 ,  H01L24/09 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2924/10253 ,  H01L2924/14 ,  H05K1/0296 ,  H05K1/111 ,  H05K1/115

Abstract: Semiconductor packages having variable redistribution layer thicknesses are described. In an example, a semiconductor package includes a redistribution layer on a dielectric layer, and the redistribution layer includes first conductive traces having a first thickness and second conductive traces having a second thickness. The first thickness may be different than the second thickness, e.g., the first thickness may be less than the second thickness.