公开(公告)号：US07615866B2

公开(公告)日：2009-11-10

申请号：US11419798

申请日：2006-05-23

Applicant: James Jen-Ho Wang ,  Paul T. Hui

Inventor： James Jen-Ho Wang ,  Paul T. Hui

IPC: H01L23/48 ,  H01L23/52

CPC classification number: H01L21/76801 ,  H01L24/03 ,  H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/04042 ,  H01L2224/05073 ,  H01L2224/05166 ,  H01L2224/05556 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/45144 ,  H01L2224/48463 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/14 ,  H01L2924/19043 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A semiconductor device has contact between the last interconnect layer and the bond pad that includes a barrier metal between the bond pad and the last interconnect layer. Both a passivation layer and a polyimide layer separate the last interconnect layer and the bond pad. The passivation layer is patterned to form a first opening to contact the last interconnect layer. The polyimide layer is also patterned to leave a second opening that is inside and thus smaller than the first opening through the passivation. The barrier layer is then deposited in contact with the last interconnect layer and bounded by the polyimide layer. The bond pad is then formed in contact with the barrier, and a wire bond is then made to the bond pad.

Abstract translation: 半导体器件在最后的互连层和包含接合焊盘和最后互连层之间的阻挡金属的接合焊盘之间具有接触。 钝化层和聚酰亚胺层都分离最后的互连层和接合焊盘。 图案化钝化层以形成第一开口以接触最后的互连层。 聚酰亚胺层也被图案化以留下内部的第二开口，因此比通过钝化的第一开口小。 然后将阻挡层沉积成与最后的互连层接触并且被聚酰亚胺层界定。 然后将接合焊盘形成为与阻挡层接触，然后对接合焊盘进行引线接合。

公开(公告)号：US20090065904A1

公开(公告)日：2009-03-12

申请号：US11851857

申请日：2007-09-07

Applicant: James Jen-Ho Wang

Inventor： James Jen-Ho Wang

IPC: H01L23/52 ,  H01L21/44

CPC classification number: H01L25/50 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/16225 ,  H01L2224/48227 ,  H01L2224/73257 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/00

Abstract: An annular trench region is formed at a semiconductor substrate of an electronic device that defines a conductive plug of the through-wafer via, wherein the conductive plug includes an undisturbed portion of the semiconductor substrate.

Abstract translation: 环形沟槽区形成在限定贯通晶片通孔的导电插塞的电子器件的半导体衬底上，其中导电插塞包括半导体衬底的未受干扰的部分。

公开(公告)号：US5860585A

公开(公告)日：1999-01-19

申请号：US658907

申请日：1996-05-31

Applicant: James L. Rutledge ,  Kenneth Kaskoun ,  James Jen-Ho Wang

Inventor： James L. Rutledge ,  Kenneth Kaskoun ,  James Jen-Ho Wang

IPC: H01L21/60 ,  H01L23/485 ,  H05K3/34

CPC classification number: H01L24/13 ,  H01L24/11 ,  H05K3/3473 ,  H01L2224/11003 ,  H01L2224/11334 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2924/0001 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H05K2201/10674 ,  H05K2203/0338 ,  H05K2203/0726 ,  H05K2203/1476 ,  Y10T156/1089 ,  Y10T428/12417 ,  Y10T428/12486 ,  Y10T428/12528 ,  Y10T428/12597 ,  Y10T428/21 ,  Y10T428/23921 ,  Y10T428/2933

Abstract: A first pattern of bumps and a second pattern of bumps are formed on a substrate (10) with bumps (14,15). During a transfer process, only the bumps (14) of the first pattern of bumps are transferred to pad extensions (20) of a device (17). The bumps (15) of the second pattern of bumps are not affected by this process and can be later transferred to a second device.

公开(公告)号：US5084407A

公开(公告)日：1992-01-28

申请号：US709928

申请日：1991-06-03

Applicant: Bernard W. Boland ,  Barbara Vasquez ,  James Jen-Ho Wang

Inventor： Bernard W. Boland ,  Barbara Vasquez ,  James Jen-Ho Wang

IPC: H01L21/76 ,  H01L21/20 ,  H01L21/306 ,  H01L21/3105 ,  H01L21/762

CPC classification number: H01L21/02024 ,  H01L21/02381 ,  H01L21/02395 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/31053 ,  H01L21/76294 ,  Y10S438/969 ,  Y10S438/977

Abstract: A method is described for planarizing isolated regions (12) and active regions (22) of a semiconductor wafer (10). Semiconductor wafer (10) is provided with islands of dielectric (12) that cover portions of the semiconductor wafer (10), while leaving other portions of the semiconductor wafer (10) exposed. The dielectric islands (12) have a polysilicon layer (13) that covers the dielectric islands' (12) top surface. A blanket layer of silicon is deposited on the polysilicon layer (13) that covers the top surface of the dielectric islands and is deposited between the dielectric islands (12). Planarizing the blanket layer of epitaxial silicon is achieved by a chemical-mechanical means, thereby producing a planar surface of isolated areas (12) and active areas (22).

Abstract translation: 描述了用于平坦化半导体晶片（10）的隔离区域（12）和有源区域（22）的方法。 半导体晶片（10）设置有覆盖半导体晶片（10）的部分的绝缘体岛，同时使半导体晶片（10）的其它部分露出。 电介质岛（12）具有覆盖介电岛（12）顶表面的多晶硅层（13）。 在覆盖电介质岛的顶表面的多晶硅层（13）上沉积硅层，并沉积在介质岛（12）之间。 通过化学机械装置实现平面化外延硅的覆盖层，由此产生隔离区域（12）和有源区域（22）的平坦表面。