Abstract:
An exemplary serial peripheral interface circuit includes a host, a plurality of slaves, and a decoder. A data output terminal, a data input terminal, and a serial clock terminal of the host are connected to a data input terminal, a data output terminal, and a serial clock terminal of each slaves respectively. A slave select terminal of the host is connected to a data receive terminal of the decoder. GPIO pins of the hot are connected to corresponding input terminals of the decoder correspondingly. A select terminal of each slave is connected to a corresponding output terminal of the decoder. The address generated by the GPIO pins controls the decoder, so that the select terminal of the host can be connected to a corresponding slave device via the decoder.
Abstract:
A network status indicating circuit includes a logic circuit, a switch circuit, and an indicating unit. The logic circuit includes nine input ends, a NOT gate, and two OR gates. The switch circuit includes two input ends and two output ends. The indicating unit includes two LEDs. The logic circuit is connected to the indicating unit to indicate the status of a network IC.
Abstract:
A polarity adjusting apparatus for automatically adjusting polarity of a connection between a power supply and a charging circuit includes first˜fourth diodes, first and second input terminals configured for connecting to positive and negative terminals of the power supply, and first and second output terminals configured for respectively connecting to positive and negative input terminals of the charging circuit. The anode and cathode of the first diode are respectively connected to the first input terminal and the first output terminal. The anode and cathode of the second diode are respectively connected to the second input terminal and the first output terminal. The cathode and anode of the third diode are respectively connected to the first input terminal and the second output terminal. The cathode and anode of the fourth diode are respectively connected to the second input terminal and the second output terminal.
Abstract:
A simple network management protocol (SNMP) management card includes a processor, a network interface card (NIC) chip, a network port connected to the processor via the NIC chip, a power sourcing equipment (PSE) chip, and a power port connected to the network port via the PSE chip. The network port is configured to be connected to a network device. The PSE chip receives power from the power port and transmits the power to the network device via the network port.
Abstract:
A fan detecting apparatus for detecting at least two fans includes a processing unit, at least two airflow switches, and at least two indicating units. The processing unit includes a first terminal configured to output a driving signal, a second terminal configured to receive the driving signal, and a third terminal, the processing unit alarming when the second terminal does not receive the driving signal from the first terminal. The at least two airflow switches are serially coupled between the first and second terminals, monitor airflow from at least two fans in a computer room, and turn on or off according to strength of airflow from the at least two fans. The indicating units are respectively coupled between corresponding airflow switches and the third terminal of the processing unit, and indicate status of corresponding fans according to on or off status of the airflow switches.
Abstract:
An airflow detecting apparatus for a fan includes an amplifier circuit (100), a comparator circuit (200), a micro control unit (MCU) (U1), and an indicating circuit (300). The amplifier circuit has an input terminal receiving a voltage signal from a piezoelectric film (H1) disposed at an airflow path of the fan, and outputs an amplified voltage signal at an output terminal. The comparator circuit has an input terminal receiving the amplified voltage signal from the amplifier circuit and compares the amplified voltage signal with a reference voltage signal received at another input terminal of the comparator circuit, and outputs a voltage level signal at an output terminal. The MCU receives the voltage level signal from the comparator circuit and processes it to output an indicating signal. The indicating circuit receives the indicating signal from the MCU and indicates status of airflow.
Abstract:
A reset device for a computer system is provided. The reset device includes a hardware-reset signal generating circuit for outputting a hardware-reset signal to reset the computer system; a switch connected to the hardware-reset signal generating circuit, the hardware-reset signal generating circuit outputting the hardware-reset signal when the switch is on; a timing circuit set for outputting a controlling signal after a predetermined time that the switch has been on has passed; and a latch circuit communicating with a central processing unit (CPU) of the computer system and the timing circuit, the latch circuit latching the controlling signal and delivering the controlling signal to the CPU, the CPU controlling system settings to resume default values based on the controlling signal.
Abstract:
A PCB assembly includes a motherboard, a daughter board, and an elastic strip. The motherboard is electrically connected to the daughter board via connectors. Each of the motherboard and the daughter board includes an area connected to a power layer or a ground layer. One end of the elastic strip electrically connects to the area of the motherboard. The other end of the elastic strip electrically connects to the area of the daughter board whereby increases electrically connection between the motherboard and the daughter board.
Abstract:
A heat dissipating assembly mounted in an enclosure of an electronic device for dissipating heat for an electronic component of the electronic device, includes a heat sink attached to the electronic component of the electronic device, and a heat-conducting member connecting the enclosure of the electronic device and the heat sink so as to conducting heat from the heat sink to the enclosure.
Abstract:
A chip includes a plurality of pins; and a plurality of symbols defined on a surface of the chip, wherein the symbols are arranged as a graduated scale corresponding with the pins. It becomes very easy to find a initial pin from among the plurality of pins of the chip.