公开(公告)号：US20070231960A1

公开(公告)日：2007-10-04

申请号：US11731140

申请日：2007-03-30

Applicant: Mark Pavier ,  Andy Farlow

Inventor： Mark Pavier ,  Andy Farlow

IPC: H01L21/00

CPC classification number: H01L24/33 ,  B23K1/0006 ,  B23K1/0016 ,  B23K35/0244 ,  B23K35/025 ,  B23K2101/42 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L2224/16 ,  H01L2224/29 ,  H01L2224/291 ,  H01L2224/29111 ,  H01L2224/29113 ,  H01L2224/29124 ,  H01L2224/29139 ,  H01L2224/29147 ,  H01L2224/29188 ,  H01L2224/2929 ,  H01L2224/29311 ,  H01L2224/29313 ,  H01L2224/29324 ,  H01L2224/29339 ,  H01L2224/29347 ,  H01L2224/29388 ,  H01L2224/32245 ,  H01L2224/325 ,  H01L2224/73153 ,  H01L2224/83232 ,  H01L2224/83801 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01077 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/0133 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/157 ,  H01L2924/1579 ,  H01L2924/3011 ,  H01L2924/01083 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A process for fabricating a semiconductor package which includes using an exothermically active nanoparticle paste to join an electrode of a semiconductor die to a support body.

Abstract translation: 一种制造半导体封装的方法，其包括使用放热活性纳米粒子糊将半导体管芯的电极连接到支撑体。

公开(公告)号：US07250672B2

公开(公告)日：2007-07-31

申请号：US10987697

申请日：2004-11-12

Applicant: Mark Pavier ,  Ajit Dubhashi ,  Jorge Cerezo ,  Leigh Cormie ,  Vijay Bolloju

Inventor： Mark Pavier ,  Ajit Dubhashi ,  Jorge Cerezo ,  Leigh Cormie ,  Vijay Bolloju

IPC: H01L23/52

CPC classification number: H01L24/49 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/48 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49111 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01031 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: A semiconductor package that includes two semiconductor die each disposed on a respective die pad and a large tracking distance interposed between at least two leads of the package for better creepage characteristics.

Abstract translation: 一种半导体封装，其包括两个半导体管芯，每个半导体管芯设置在相应的管芯焊盘上，并且具有大的跟踪距离，插入在封装的至少两个引线之间，以获得更好的爬

公开(公告)号：US07235877B2

公开(公告)日：2007-06-26

申请号：US11231690

申请日：2005-09-21

Applicant: Mark Pavier

Inventor： Mark Pavier

IPC: H01L23/043

CPC classification number: H01L24/97 ,  H01L23/04 ,  H01L23/24 ,  H01L24/83 ,  H01L2224/04105 ,  H01L2224/291 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/32257 ,  H01L2224/73153 ,  H01L2224/73267 ,  H01L2224/83801 ,  H01L2224/83851 ,  H01L2224/97 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/07802 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15156 ,  H01L2924/16152 ,  H01L2924/0665 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A semiconductor package has a thinned semiconductor die fixed in a shallow opening in a conductive body. The die electrodes at the bottom of the die are plated with a redistributed contact which overlaps the die bottom contact and an insulation body which fills the annular gap between the die and opening. A process is described for the manufacture of the package in which plural spaced openings in a lead frame body and are simultaneously processed and singulated at the end of the process.

Abstract translation: 半导体封装具有固定在导电体中的浅开口中的变薄的半导体管芯。 模具底部的裸片电极被电镀有重新分布的接触件，该接触件与模具底部接触件重叠，并且绝缘体填充了模具和开口之间的环形间隙。 描述了用于制造包装的方法，其中引线框体中的多个间隔开的开口在工艺结束时被同时处理和分割。

公开(公告)号：US20070099343A1

公开(公告)日：2007-05-03

申请号：US11592408

申请日：2006-11-03

Applicant: Mark Pavier

Inventor： Mark Pavier

IPC: H01L21/00

CPC classification number: H01L24/97 ,  H01L2224/16 ,  H01L2224/16245 ,  H01L2224/73153 ,  H01L2224/97 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/181 ,  Y10T436/19 ,  Y10T436/20 ,  H01L2224/81 ,  H01L2924/00

Abstract: A method for fabricating a semiconductor package which includes coupling an electrode of a semiconductor device to a portion of a lead frame, overmolding at least a portion of the die, and then removing a portion of the die to obtain a desired thickness.

Abstract translation: 一种制造半导体封装的方法，包括将半导体器件的电极耦合到引线框架的一部分，包覆模制至少一部分模具，然后去除模具的一部分以获得期望的厚度。

公开(公告)号：US20070096274A1

公开(公告)日：2007-05-03

申请号：US11591834

申请日：2006-11-02

Applicant: Mark Pavier ,  David Bushnell

Inventor： Mark Pavier ,  David Bushnell

IPC: H01L23/495

CPC classification number: H01L25/162 ,  H01L25/072 ,  H01L2224/73153 ,  H01L2924/01077 ,  H01L2924/01079 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/00

Abstract: An insulated metal substrate composite has a patterned conductive layer on one surface and receives one or more electrodes of MOSFETs or other die on the patterned segments which lead to the edge of the IMS. The outer periphery of the IMS is cupped or bent to form a shallow can with two or more die fixed to and thermally coupled to the flat web of the can while electrodes on the die surfaces thermally coupled to the web of the can lead to terminals on the rim of the can which are coplanar with the bottom surfaces of the die. The electrodes can be externally or internally connected to form a half bridge circuit.

Abstract translation: 绝缘金属衬底复合材料在一个表面上具有图案化的导电层，并且在图案化区段上接收通向IMS边缘的一个或多个MOSFET电极或其它管芯。 IMS的外围被杯形或弯曲以形成一个浅的罐，其中两个或多个管芯被固定并且热耦合到罐的扁平腹板上，而与模具表面热耦合的模具表面上的电极可以导致端子 罐的边缘与模具的底表面共面。 电极可以在外部或内部连接以形成半桥电路。

公开(公告)号：US07034344B2

公开(公告)日：2006-04-25

申请号：US10888410

申请日：2004-07-08

Applicant: Mark Pavier ,  Tim Sammon ,  Chris Davis

Inventor： Mark Pavier ,  Tim Sammon ,  Chris Davis

IPC: H01L27/02

CPC classification number: H01L24/81 ,  H01L23/4824 ,  H01L2224/81801 ,  H01L2924/01005 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/13091 ,  H01L2924/00

Abstract: An integrated semiconductor device which includes a plurality of power semiconductor devices formed in a common semiconductor die.

Abstract translation: 一种集成半导体器件，包括形成在公共半导体管芯中的多个功率半导体器件。

公开(公告)号：US20060060891A1

公开(公告)日：2006-03-23

申请号：US11231690

申请日：2005-09-21

Applicant: Mark Pavier

Inventor： Mark Pavier

IPC: H01L27/148

CPC classification number: H01L24/97 ,  H01L23/04 ,  H01L23/24 ,  H01L24/83 ,  H01L2224/04105 ,  H01L2224/291 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/32257 ,  H01L2224/73153 ,  H01L2224/73267 ,  H01L2224/83801 ,  H01L2224/83851 ,  H01L2224/97 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/07802 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15156 ,  H01L2924/16152 ,  H01L2924/0665 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A semiconductor package has a thinned semiconductor die fixed in a shallow opening in a conductive body. The die electrodes at the bottom of the die are plated with a redistributed contact which overlaps the die bottom contact and an insulation body which fills the annular gap between the die and opening. A process is described for the manufacture of the package in which plural spaced openings in a lead frame body and are simultaneously processed and singulated at the end of the process.

Abstract translation: 半导体封装具有固定在导电体中的浅开口中的变薄的半导体管芯。 模具底部的裸片电极被电镀有重新分布的接触件，该接触件与模具底部接触件重叠，并且绝缘体填充了模具和开口之间的环形间隙。 描述了用于制造包装的方法，其中引线框体中的多个间隔开的开口在工艺结束时被同时处理和分割。

公开(公告)号：US20050207133A1

公开(公告)日：2005-09-22

申请号：US11078807

申请日：2005-03-11

Applicant: Mark Pavier ,  Tim Sammon

Inventor： Mark Pavier ,  Tim Sammon

IPC: G06F1/16 ,  H05K1/14 ,  H05K1/18 ,  H05K3/34

CPC classification number: H05K1/141 ,  H01L24/24 ,  H01L24/82 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/2518 ,  H01L2924/13055 ,  H01L2924/13063 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/19105 ,  H05K1/185 ,  H05K3/3436 ,  H05K2201/10734 ,  H01L2924/00

Abstract: A peripheral electronic system for an electronic device including a motherboard having multiple individual electrically connected vertically stacked modules, at least one of which is a circuit board assembly including active and/or passive electronic components embedded therein with the components being electrically connected by conductive traces to provide desired operating function. The peripheral electronic system further includes an electrical connector array on an exposed surface of the composite structure to provide electrical connections between the peripheral electronic system and the motherboard.

Abstract translation: 一种用于电子设备的外围电子系统，包括具有多个单独电连接的垂直堆叠模块的母板，其中至少一个是包括嵌入其中的有源和/或无源电子元件的电路板组件，其中所述元件通过导电迹线电连接到 提供所需的操作功能。 外围电子系统还包括在复合结构的暴露表面上的电连接器阵列，以提供外围电子系统和母板之间的电连接。

公开(公告)号：US06894397B2

公开(公告)日：2005-05-17

申请号：US10260148

申请日：2002-09-27

Applicant: Mark Pavier ,  Tim Sammon

Inventor： Mark Pavier ,  Tim Sammon

IPC: H01L23/34 ,  H01L21/60 ,  H01L23/367 ,  H01L23/52 ,  H01L27/088 ,  H01L29/78 ,  H01L23/48 ,  H01L29/40

CPC classification number: H01L29/7811 ,  H01L23/3677 ,  H01L24/81 ,  H01L27/088 ,  H01L29/7809 ,  H01L29/7813 ,  H01L2224/81801 ,  H01L2924/01068 ,  H01L2924/10253 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/00

Abstract: A flip chip structure contains laterally spaced semiconductor devices such as MOSFETs in a common chip. A deep trench isolates the devices. Contacts are connected to the source drain and gate electrode (or other electrodes) and are interconnected as required for a circuit function either within the chip or on the support board. Ball contacts are connected to the electrodes. The opposite surface of the chip to that in which the devices are formed receives a copper or other metal layer which is patterned to increase its area for heat exchange. The surface of the copper is coated with black oxide to increase its ability to radiate heat.

Abstract translation: 倒装芯片结构包含横向​​间隔的半导体器件，例如公共芯片中的MOSFET。 深沟渠隔离设备。 触点连接到源极漏极和栅电极（或其他电极），并且根据芯片或支撑板上的电路功能的要求进行互连。 球触点连接到电极。 芯片的与形成器件的相对表面接收铜或其它金属层，其被图案化以增加其用于热交换的面积。 铜的表面涂覆有黑色氧化物以增加其辐射热能力。

公开(公告)号：US06858922B2

公开(公告)日：2005-02-22

申请号：US10050002

申请日：2002-01-15

Applicant: Mark Pavier

Inventor： Mark Pavier

IPC: H01L23/495

CPC classification number: H01L24/49 ,  H01L23/49575 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49111 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A small footprint package for two or more semiconductor die includes first and second die, mounted on opposite respective surfaces of a lead frame pad in vertical alignment with one another. A conductive or insulation adhesive can be used. The die can be identical MOSgated devices connected in series, or can be one power die and a second IC die for the control of the power die.

Abstract translation: 用于两个或更多个半导体管芯的小尺寸封装包括第一和第二管芯，其安装在彼此垂直对准的引线框架焊盘的相对的相对表面上。 可以使用导电或绝缘粘合剂。 芯片可以是串联连接的相同的MOS器件，或者可以是一个功率管芯和用于控制功率管芯的第二个IC管芯。