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    Fabricating Memory Devices with Optimized Gate Oxide Thickness
    31.
    发明申请
    Fabricating Memory Devices with Optimized Gate Oxide Thickness 审中-公开

    公开(公告)号：US20190259768A1

    公开(公告)日：2019-08-22

    申请号：US16397943

    申请日：2019-04-29

    Applicant: Marvell World Trade Ltd.

    Inventor： Runzi Chang ,  Winston Lee ,  Peter Lee

    IPC: H01L27/112 ,  H01L29/423 ,  H01L23/525 ,  G11C17/16 ,  H01L21/02 ,  H01L21/311 ,  G11C17/18 ,  H01L21/027

    Abstract: The present disclosure describes apparatuses and methods for manufacturing programmable memory devices with optimized gate oxide thickness. In some aspects, lithography masks are used to fabricate oxide gates for programmable memory devices of an integrated-circuit (IC) die that are thinner than oxide gates fabricated for processor core devices of the IC die. In other aspects, lithography masks are used to fabricate oxide gates for the programmable memory devices of the IC die such that they are thicker than the oxide gates fabricated for the processor core devices of the IC die. By so doing, the programmable memory devices can be manufactured with optimized gate oxide thickness that may reduce programming voltage or increase device reliability of the programmable memory devices.

    Method and apparatus for reforming a memory cell of a memory
    32.
    发明授权
    Method and apparatus for reforming a memory cell of a memory 有权
    用于重构存储器的存储单元的方法和装置

    公开(公告)号：US09129678B2

    公开(公告)日：2015-09-08

    申请号：US14536761

    申请日：2014-11-10

    Applicant: Marvell World Trade Ltd.

    Inventor： Pantas Sutardja ,  Albert Wu ,  Winston Lee ,  Peter Lee ,  Runzi Chang

    IPC: G11C7/00 ,  G11C13/00 ,  G11C29/50 ,  G11C11/16

    CPC classification number: G11C13/0069 ,  G11C11/16 ,  G11C13/00 ,  G11C13/0033 ,  G11C13/004 ,  G11C29/50008 ,  G11C2013/0076 ,  G11C2013/0083

    Abstract: A memory including a memory cell and first and second modules. The memory cell has first and second states, where the second state is different than the first state. The first module, subsequent to an initial forming of the memory cell and subsequent to a read cycle or a write cycle of the memory cell, determines a first difference between the first state and a first predetermined threshold or a second difference between the first state and the second state. The second module, subsequent to the first module determining the first difference or the second difference, reforms the memory cell to reset and increase the first difference or the second difference. The second module, during the reforming of the memory cell, applies a first voltage to the memory cell. The first voltage is greater than a voltage applied to the memory cell during the read cycle or the write cycle.

    Abstract translation: 包括存储单元和第一和第二模块的存储器。 存储单元具有第一状态和第二状态，其中第二状态不同于第一状态。 第一模块在初始形成存储器单元之后并且在存储器单元的读取周期或写入周期之后，确定第一状态和第一预定阈值之间的第一差异，或者第一状态与第一状态和 第二个状态。 第二模块在第一模块确定第一差异或第二差异之后，改变存储器单元以复位并增加第一差值或第二差值。 第二模块在存储单元重整期间向存储单元施加第一电压。 在读周期或写周期期间，第一电压大于施加到存储单元的电压。

    CONFIGURING RESISTIVE RANDOM ACCESS MEMORY (RRAM) ARRAY FOR WRITE OPERATIONS
    33.
    发明申请
    CONFIGURING RESISTIVE RANDOM ACCESS MEMORY (RRAM) ARRAY FOR WRITE OPERATIONS 有权
    配置电阻随机访问存储器（RRAM）阵列进行写操作

    公开(公告)号：US20140104927A1

    公开(公告)日：2014-04-17

    申请号：US14050696

    申请日：2013-10-10

    Applicant: Marvell World Trade Ltd.

    Inventor： Pantas Sutardja ,  Albert Wu ,  Runzi Chang ,  Winston Lee ,  Peter Lee

    IPC: G11C13/00

    CPC classification number: G11C13/0069 ,  G11C13/0002 ,  G11C13/0007 ,  G11C2013/0073 ,  G11C2213/79 ,  G11C2213/82

    Abstract: A system includes a resistive random access memory cell and a driver circuit. The resistive random access memory cell includes a resistive element and a switching element, and has a first terminal connected to a bit line and a second terminal connected to a word line. The driver circuit is configured to apply, in response to selection of the resistive random access memory cell using the word line, a first voltage of a first polarity to the bit line to program the resistive random access memory cell to a first state by causing current to flow through the resistive element in a first direction, and a second voltage of a second polarity to the bit line to program the resistive random access memory cell to a second state by causing current to flow through the resistive element in a second direction.

    Abstract translation: 系统包括电阻随机存取存储单元和驱动电路。 电阻性随机存取存储单元包括电阻元件和开关元件，并且具有连接到位线的第一端子和连接到字线的第二端子。 驱动器电路被配置为响应于使用字线选择电阻性随机存取存储器单元，将第一极性的第一电压施加到位线，以通过引起电流将电阻性随机存取存储器单元编程为第一状态 沿着第一方向流过电阻元件，并向位线流过第二极性的第二电压，以通过使电流沿第二方向流过电阻元件而将电阻性随机存取存储器单元编程为第二状态。

    Creating an aligned via and metal line in an integrated circuit including forming an oversized via mask
    34.
    发明授权
    Creating an aligned via and metal line in an integrated circuit including forming an oversized via mask 有权

    公开(公告)号：US11081387B2

    公开(公告)日：2021-08-03

    申请号：US16713044

    申请日：2019-12-13

    Applicant: Marvell World Trade Ltd.

    Inventor： Runzi Chang ,  Min She

    IPC: H01L21/768 ,  H01L21/027 ,  H01L21/033 ,  H01L21/67 ,  H01L21/02 ,  H01L21/311 ,  H01L21/288

    Abstract: A method of forming an integrated circuit includes: forming a dielectric layer, a hard mask layer, a film layer and a photoresist layer; and patterning the photoresist layer to form a via mask, where the via mask is oversized, such that the via mask extends across opposing sides of a metal line mask in the hard mask layer. The method further includes: etching the film layer and the dielectric layer based on the patterned photoresist layer; ashing the photoresist layer and the film layer; etching the dielectric layer based on a pattern of the hard mask layer to provide a via region and a metal line region; etching the hard mask layer and the dielectric layer; and performing a plurality of dual damascene process operations to form a via in the via region and a metal line in the metal line region in the integrated circuit.

    Fabricating memory devices with optimized gate oxide thickness
    35.
    发明授权
    Fabricating memory devices with optimized gate oxide thickness 有权

    公开(公告)号：US10319727B2

    公开(公告)日：2019-06-11

    申请号：US15799776

    申请日：2017-10-31

    Applicant: Marvell World Trade Ltd.

    Inventor： Runzi Chang ,  Winston Lee ,  Peter Lee

    IPC: G11C17/18 ,  H01L21/02 ,  H01L21/027 ,  H01L21/311 ,  H01L27/112 ,  H01L29/423 ,  G11C17/16 ,  H01L23/525

    Abstract: The present disclosure describes apparatuses and methods for manufacturing programmable memory devices with optimized gate oxide thickness. In some aspects, lithography masks are used to fabricate oxide gates for programmable memory devices of an integrated-circuit (IC) die that are thinner than oxide gates fabricated for processor core devices of the IC die. In other aspects, lithography masks are used to fabricate oxide gates for the programmable memory devices of the IC die such that they are thicker than the oxide gates fabricated for the processor core devices of the IC die. By so doing, the programmable memory devices can be manufactured with optimized gate oxide thickness that may reduce programming voltage or increase device reliability of the programmable memory devices.

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