公开(公告)号：US11862221B2

公开(公告)日：2024-01-02

申请号：US17830100

申请日：2022-06-01

Applicant: Micron Technology, Inc.

Inventor： Angelo Visconti

IPC: G11C11/22

CPC classification number: G11C11/2297 ,  G11C11/221

Abstract: Methods, systems, and devices for switch and hold biasing for memory cell imprint recovery are described. A memory device may be configured to perform an imprint recovery procedure that includes applying one or more recovery pulses to memory cells, where each recovery pulse is associated with a voltage polarity and includes a first portion with a first voltage magnitude and a second portion with a second voltage magnitude that is lower than the first voltage magnitude. In some examples, the first voltage magnitude may correspond to a voltage that imposes a saturation polarization on a memory cell (e.g., on a ferroelectric capacitor, a polarization corresponding to the associated voltage polarity) and the second voltage magnitude may correspond to a voltage magnitude that is high enough to maintain the saturation polarization (e.g., to prevent a reduction of polarization) of the memory cell.

公开(公告)号：US20230350582A1

公开(公告)日：2023-11-02

申请号：US17730777

申请日：2022-04-27

Applicant: Micron Technology, Inc.

Inventor： Angelo Visconti ,  Jahanshir Javanifard ,  Daniele Vimercati

IPC: G06F3/06

CPC classification number: G06F3/0623 ,  G06F3/0655 ,  G06F3/0679

Abstract: Methods, systems, and devices for data masking for memory are described. A memory device may set multiple data masking flags for associated memory array(s) at power-up. Each data masking flag may be associated with a respective page of memory cells and may indicate whether the data stored in the respective page is masked data, or whether the data is new, unmasked data. Data existing at a previous power-down may be masked until an initial write or activate command has been performed on the page after power-up, where the initial write or activate command may result in writing masked data, write data, or a combination thereof to the page. After previously stored data is overwritten to a page, the flag associated with the page may be reset, which may indicate that data stored at the page is available to be read.

公开(公告)号：US11721379B2

公开(公告)日：2023-08-08

申请号：US17350771

申请日：2021-06-17

Applicant: Micron Technology, Inc.

Inventor： Angelo Visconti ,  Jahanshir J. Javanifard

IPC: G11C11/22

CPC classification number: G11C11/2297 ,  G11C11/221 ,  G11C11/2275

Abstract: Methods, systems, and devices for cell data bulk reset are described. In some examples, a write pulse may be applied to one or more memory cells based on an associated memory device transitioning power states. To apply the wire pulse, a first subset of digit lines may be driven to a first voltage and a plate may be driven to a second voltage or a third voltage. While the digit lines and plate are driven to the respective voltages, one or more word lines may be driven to the second voltage or the third voltage. In some instances, the digit lines may be selected (e.g., driven) according to a pattern.

公开(公告)号：US20230222042A1

公开(公告)日：2023-07-13

申请号：US17575399

申请日：2022-01-13

Applicant: Micron Technology, Inc.

Inventor： Angelo Visconti ,  John David Porter

IPC: G06F11/30 ,  G11C5/14

CPC classification number: G06F11/3058 ,  G06F11/3055 ,  G06F11/3037 ,  G11C5/14

Abstract: Systems and methods described herein may enable memory maintenance operations to be performed on a memory device in compliance with a time interval having a duration based on a temperature of the memory device. A system may include a memory device and a memory controller communicatively coupled to the memory device. The memory controller may receive a temperature measurement indicative of a present temperature of the memory device and determine a memory management interval based on the temperature measurement. The memory controller may perform a memory management operation based on the memory management interval. Sometimes, the memory controller powers on the memory device to perform the memory management operation on the memory device.

公开(公告)号：US20230114735A1

公开(公告)日：2023-04-13

申请号：US18053305

申请日：2022-11-07

Applicant: Micron Technology, Inc.

Inventor： Angelo Visconti ,  Riccardo Pazzocco ,  Jonathan J. Strand ,  Kevin T. Majerus

IPC: G11C11/22 ,  G11C29/50

Abstract: Methods, systems, and devices for charge leakage detection for memory system reliability are described. In accordance with examples as disclosed herein, a memory system may employ memory management techniques configured to identify precursors of charge leakage in a memory device, and take preventative action based on such identified precursors. For example, a memory system may be configured to perform a leakage detection evaluation for a memory array, which may include various biasing and evaluation operations to identify whether a leakage condition of the memory array may affect operational reliability. Based on such an evaluation, the memory device, or a host device in communication with the memory device, may take various preventative measures to avoid operational failures of the memory device or host device that may result from ongoing operation of a memory array associated with charge leakage, thereby improving reliability of the memory system.

公开(公告)号：US11514968B2

公开(公告)日：2022-11-29

申请号：US16831524

申请日：2020-03-26

Applicant: Micron Technology, Inc.

Inventor： Angelo Visconti ,  Riccardo Pazzocco ,  Jonathan J. Strand ,  Kevin T. Majerus

IPC: G11C11/22 ,  G11C29/50

Abstract: Methods, systems, and devices for charge leakage detection for memory system reliability are described. In accordance with examples as disclosed herein, a memory system may employ memory management techniques configured to identify precursors of charge leakage in a memory device, and take preventative action based on such identified precursors. For example, a memory system may be configured to perform a leakage detection evaluation for a memory array, which may include various biasing and evaluation operations to identify whether a leakage condition of the memory array may affect operational reliability. Based on such an evaluation, the memory device, or a host device in communication with the memory device, may take various preventative measures to avoid operational failures of the memory device or host device that may result from ongoing operation of a memory array associated with charge leakage, thereby improving reliability of the memory system.

公开(公告)号：US20220300375A1

公开(公告)日：2022-09-22

申请号：US17714777

申请日：2022-04-06

Applicant: Micron Technology, Inc.

Inventor： Richard E. Fackenthal ,  Angelo Visconti

IPC: G06F11/10 ,  G11C11/22 ,  G11C11/4091

Abstract: Methods, systems, and devices for erasure decoding for a memory device are described. In accordance with the described techniques, a memory device may be configured to identify conditions associated with an erasure, a possible erasure, or an otherwise indeterminate logic state (e.g., of a memory cell, of an information position of a codeword). Such an identification may be used to enhance aspects of error handling operations, including those that may be performed at the memory device or a host device (e.g., error handling operations performed at a memory controller external to the memory device). For example, error handling operations may be performed using speculative codewords, where information positions associated with an indeterminate or unassigned logic state are assigned with a respective assumed logic state, which may extend a capability of error detection or error correction compared to handling errors with unknown positions.

公开(公告)号：US20220270667A1

公开(公告)日：2022-08-25

申请号：US17741136

申请日：2022-05-10

Applicant: Micron Technology, Inc.

Inventor： Andrea Locatelli ,  Giorgio Servalli ,  Angelo Visconti

IPC: G11C11/4096 ,  G11C11/22 ,  G11C11/4097 ,  G11C11/406 ,  G11C11/4091

Abstract: Methods, systems, and devices for biasing a memory cell during a read operation are described. For example, a memory device may bias a memory cell to a first voltage (e.g., a read voltage) during an activation phase of a read operation. After biasing the memory cell to the first voltage, the memory device may bias the memory cell to a second voltage greater than the first voltage (e.g., a write voltage) during the activation phase of the read operation. After biasing the memory cell to the second voltage, the memory device may initiate a refresh phase of the read operation. Based on a value stored by the memory cell prior to biasing the memory cell to the first voltage, the memory device may initiate a precharge phase of the read operation.

公开(公告)号：US20220199138A1

公开(公告)日：2022-06-23

申请号：US17690614

申请日：2022-03-09

Applicant: Micron Technology, Inc.

Inventor： Angelo Visconti

IPC: G11C11/22

Abstract: Methods, systems, and devices for techniques to mitigate asymmetric long delay stress are described. A memory device may activate a memory cell during a first phase of an access operation cycle. The memory device may write a first state or a second state to the memory cell during the first phase of the access operation cycle. The memory device may maintain the first state or the second state during a second phase of the access operation cycle after the first phase of the access operation cycle. The memory device may write, during a third phase of the access operation cycle after the second phase of the access operation cycle, the second state to the memory cell. The memory device may precharge the memory cell during the third phase of the access operation cycle based on writing the second state to the memory cell.

公开(公告)号：US20220197564A1

公开(公告)日：2022-06-23

申请号：US17550297

申请日：2021-12-14

Applicant: Micron Technology, Inc.

Inventor： Angelo Visconti ,  Daniele Balluchi ,  Giorgio Servalli

IPC: G06F3/06

Abstract: Systems, apparatuses, and methods related to memory activation timing management are described herein. In an examples, memory activation timing management can include receiving a first command associated with a set of memory cells, activating the set of memory cells to perform a memory access responsive to the first command, pre-charging the set of memory cells associated with the first command, receiving a second command associated with the set of memory cells, determining that the set of memory cells associated with the first command is a recently activated set of the plurality of sets of memory cells, imparting a delay, and applying a sensing voltage to the set of memory cells associated with the second command to perform a memory access responsive to the second command.