公开(公告)号：US10956053B2

公开(公告)日：2021-03-23

申请号：US16209007

申请日：2018-12-04

Applicant: Micron Technology, Inc.

Inventor： Ashutosh Malshe ,  Kishore Kumar Muchherla ,  Vamsi Pavan Rayaprolu ,  Harish R. Singidi

IPC: G06F3/00 ,  G06F3/06 ,  G06F16/23

Abstract: A data integrity check is performed on a data block of the memory component to obtain a reliability statistic for each of a set of sampled memory cells in the data block. A distribution statistic is determined based on the reliability statistic for each of the set of sampled memory cells. A subset of the data block is identified to be relocated to another data block of the memory component based on the distribution statistic. Data of the subset of the data block is relocated to the other data block.

公开(公告)号：US10942796B2

公开(公告)日：2021-03-09

申请号：US16544190

申请日：2019-08-19

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Michael G. Miller ,  Ashutosh Malshe ,  Violante Moschiano ,  Peter Feeley ,  Gary F. Besinga ,  Sampath K. Ratnam ,  Walter Di-Francesco ,  Renato C. Padilla, Jr. ,  Yun Li ,  Kishore Kumar Muchherla

IPC: G11C11/34 ,  G06F11/07 ,  G06F3/06 ,  G06F11/10 ,  G11C11/56 ,  G11C16/10 ,  G11C16/22 ,  G11C16/30 ,  G11C16/34 ,  G11C5/14

Abstract: Apparatus having an array of memory cells include a controller configured to read a particular memory cell of a last written page of memory cells of a block of memory cells of the array of memory cells, determine whether a threshold voltage of the particular memory cell is less than a particular voltage level, and mark the last written page of memory cells as affected by power loss during a programming operation of the last written page of memory cells when the threshold voltage of the particular memory cell is determined to be higher than the particular voltage level.

公开(公告)号：US20200335172A1

公开(公告)日：2020-10-22

申请号：US16920154

申请日：2020-07-02

Applicant: Micron Technology, Inc.

Inventor： Harish Reddy Singidi ,  Kishore Kumar Muchherla ,  Gianni Stephen Alsasua ,  Ashutosh Malshe ,  Sampath Ratnam ,  Gary F. Besinga ,  Micheal G. Miller

IPC: G11C16/26 ,  G11C16/34 ,  G11C11/56

Abstract: Disclosed in some examples, are methods, systems, and machine readable mediums which compensate for read-disturb effects by shifting the read voltages used to read the value in a NAND cell based upon a read counter. For example, the NAND memory device may have a read counter that corresponds to a group of NAND cells (e.g., a page, a block, a superblock). Anytime a NAND cell in the group is read, the read counter may be incremented. The read voltage, Vread, may be adjusted based on the read counter to account for the read disturb voltage.

公开(公告)号：US20200278814A1

公开(公告)日：2020-09-03

申请号：US16878304

申请日：2020-05-19

Applicant: Micron Technology,Inc.

Inventor： Gianni Stephen Alsasua ,  Harish Reddy Singidi ,  Peter Sean Feeley ,  Ashutosh Malshe ,  Renato Padilla, JR. ,  Kishore Kumar Muchherla ,  Sampath Ratnam

IPC: G06F3/06 ,  G11C16/34

Abstract: Systems and methods are disclosed, comprising a memory device comprising multiple groups of memory cells, the groups comprising a first group of memory cells and a second group of memory cells configured to store information at a same bit capacity per memory cell, and a processing device operably coupled to the memory device, the processing device configured to adjust a scan event threshold for one of the first or second groups of memory cells to a threshold less than a target scan event threshold for the first and second groups of memory cells to distribute scan events in time on the memory device.

公开(公告)号：US10755792B2

公开(公告)日：2020-08-25

申请号：US16448502

申请日：2019-06-21

Applicant: Micron Technology, Inc.

Inventor： Harish Reddy Singidi ,  Kishore Kumar Muchherla ,  Gianni Stephen Alsasua ,  Ashutosh Malshe ,  Sampath Ratnam ,  Gary F. Besinga ,  Michael G. Miller

IPC: G11C16/26 ,  G11C16/34 ,  G11C11/56 ,  G11C16/08 ,  G11C16/04

Abstract: Disclosed in some examples, are methods, systems, and machine readable mediums which compensate for read-disturb effects by shifting the read voltages used to read the value in a NAND cell based upon a read counter. For example, the NAND memory device may have a read counter that corresponds to a group of NAND cells (e.g., a page, a block, a superblock). Anytime a NAND cell in the group is read, the read counter may be incremented. The read voltage, Vread, may be adjusted based on the read counter to account for the read disturb voltage.

公开(公告)号：US20200210280A1

公开(公告)日：2020-07-02

申请号：US16267586

申请日：2019-02-05

Applicant: Micron Technology, Inc.

Inventor： Harish Reddy Singidi ,  Kishore Kumar Muchherla ,  Xiangang Luo ,  Vamsi Pavan Rayaprolu ,  Ashutosh Malshe

IPC: G06F11/10 ,  G06F11/14

Abstract: A variety of applications can include use of parity groups in a memory system with the parity groups arranged for data protection of the memory system. Each parity group can be structured with multiple data pages in which to write data and a parity page in which to write parity data generated from the data written in the multiple data pages. Each data page of a parity group can have storage capacity to include metadata of data written to the data page. Information can be added to the metadata of a data page with the information identifying an asynchronous power loss status of data pages that precede the data page in an order of writing data to the data pages of the parity group. The information can be used in re-construction of data in the parity group following an uncorrectable error correction code error in writing to the parity group.

公开(公告)号：US10671298B2

公开(公告)日：2020-06-02

申请号：US15913157

申请日：2018-03-06

Applicant: Micron Technology, Inc.

Inventor： Vamsi Pavan Rayaprolu ,  Sampath K. Ratnam ,  Kishore Kumar Muchherla ,  Harish R. Singidi ,  Ashutosh Malshe ,  Gianni S. Alsasua

IPC: G06F3/06

Abstract: Data to store at a storage system is received. The storage system includes data blocks and the plurality of blocks that include a first region corresponding to a first storage density and a second region corresponding to a second storage density that is less dense than the first storage density. The data is stored at the first region of the plurality of data blocks that corresponds to the first storage density. A write attribute related to storing the data at the first region of the plurality of data blocks is determined. Thereupon, the write attribute related to storing the data at the first region is stored in the second region of the plurality of data blocks that corresponds to the second storage density.

公开(公告)号：US10573357B2

公开(公告)日：2020-02-25

申请号：US16230251

申请日：2018-12-21

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar Muchherla ,  Ashutosh Malshe ,  Harish Reddy Singidi ,  Gianni Stephen Alsasua ,  Gary F. Besinga ,  Sampath Ratnam ,  Peter Sean Feeley

IPC: G11C7/00 ,  G11C7/10 ,  G11C8/10

Abstract: A variety of applications can include apparatus and/or methods of operating the apparatus that include a memory device having read levels that can be calibrated. A calibration controller implemented with the memory device can trigger a read level calibration based on inputs from one or more trackers monitoring parameters associated with the memory device and a determination of an occurrence of at least one event from a set of events related to the monitored parameters. The monitored parameters can include parameters related to a selected time interval and measurements of read, erase, or write operations of the memory device. Additional apparatus, systems, and methods are disclosed.

公开(公告)号：US10446197B2

公开(公告)日：2019-10-15

申请号：US15692407

申请日：2017-08-31

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar Muchherla ,  Ashutosh Malshe ,  Harish Singidi ,  Gianni Stephen Alsasua ,  Gary F. Besinga ,  Sampath Ratnam ,  Peter Sean Feeley

IPC: G11C7/00 ,  G11C7/10 ,  G11C8/10 ,  G11C29/02

Abstract: A variety of applications can include apparatus and/or methods of operating the apparatus that include a memory device having read levels that can be calibrated. A calibration controller implemented with the memory device can trigger a read level calibration based on inputs from one or more trackers monitoring parameters associated with the memory device and a determination of an occurrence of at least one event from a set of events related to the monitored parameters. The monitored parameters can include parameters related to a selected time interval and measurements of read, erase, or write operations of the memory device. Additional apparatus, systems, and methods are disclosed.

公开(公告)号：US20190278491A1

公开(公告)日：2019-09-12

申请号：US15913157

申请日：2018-03-06

Applicant: Micron Technology, Inc.

Inventor： Vamsi Pavan Rayaprolu ,  Sampath K. Ratnam ,  Kishore Kumar Muchherla ,  Harish R. Singidi ,  Ashutosh Malshe ,  Gianni S. Alsasua

IPC: G06F3/06

Abstract: Data to store at a storage system is received. The storage system includes data blocks and the plurality of blocks that include a first region corresponding to a first storage density and a second region corresponding to a second storage density that is less dense than the first storage density. The data is stored at the first region of the plurality of data blocks that corresponds to the first storage density. A write attribute related to storing the data at the first region of the plurality of data blocks is determined. Thereupon, the write attribute related to storing the data at the first region is stored in the second region of the plurality of data blocks that corresponds to the second storage density.