Method Used In Forming An Array Of Vertical Transistors And Method Used In Forming An Array Of Memory Cells Individually Comprising A Vertical Transistor And A Storage Device Above The Vertical Transistor

    公开(公告)号:US20220068934A1

    公开(公告)日:2022-03-03

    申请号:US17016609

    申请日:2020-09-10

    Inventor: Guangjun Yang

    Abstract: A method used in forming an array of vertical transistors comprises forming pillars individually comprising an upper source/drain region, a channel region vertically below the upper source/drain region, and sacrificial material above the upper source/drain region. Intervening material is about the sacrificial material of individual of the pillars. The intervening material and the sacrificial material comprise different compositions relative one another. Horizontally-elongated and spaced conductive gate lines are formed individually operatively aside the channel region of the individual pillars. The sacrificial material is removed to expose the upper source/drain region of the individual pillars and thereby form an opening in the intervening material directly above the upper source/drain region of the individual pillars. Metal material is formed in individual of the openings directly against the upper source/drain region of the individual pillars and atop the intervening material laterally outside of the openings. The metal material that is atop the intervening material interconnects the metal material that is in the individual openings. The metal material is removed back to have an uppermost surface that is no higher than an uppermost surface of the intervening material and to disconnect it from interconnecting the metal material that is in the individual openings and thereby form a laterally-isolated individual metal-material plug in the individual openings.

    Integrated Assemblies Having Dielectric Regions Along Conductive Structures, and Methods of Forming Integrated Assemblies

    公开(公告)号:US20200286898A1

    公开(公告)日:2020-09-10

    申请号:US16880900

    申请日:2020-05-21

    Abstract: Some embodiments include a method of forming an integrated assembly. A construction is formed to include a conductive structure having a top surface, and a pair of sidewall surfaces extending downwardly from the top surface. Insulative material is over the top surface, and rails are along the sidewall surfaces. The rails include sacrificial material. The sacrificial material is removed to leave openings. Sealant material is formed to extend within the openings. The sealant material has a lower dielectric constant than the insulative material. Some embodiments include an integrated assembly having a conductive structure with a top surface and a pair of opposing sidewall surfaces extending downwardly from the top surface. Insulative material is over the top surface. Voids are along the sidewall surfaces and are capped by sealant material. The sealant material has a lower dielectric constant than the insulative material.

    Methods of sealing openings, and methods of forming integrated assemblies

    公开(公告)号:US10418275B1

    公开(公告)日:2019-09-17

    申请号:US16369150

    申请日:2019-03-29

    Inventor: Guangjun Yang

    Abstract: Some embodiments include a method of forming an integrated assembly. A construction is formed to include a structure having an exposed surface, and to include an opening proximate the structure. An aperture extends into the opening. A first material is deposited to form a mass along the exposed surface of the structure. Particles are sputtered from the mass and across the aperture. The particles agglomerate to form a sealant material which traps a void within the opening.

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