公开(公告)号：US20230006034A1

公开(公告)日：2023-01-05

申请号：US17366557

申请日：2021-07-02

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege ,  Masihhur R. Laskar ,  Nicholas R. Tapias ,  Darwin Franseda Fan

IPC: H01L29/04 ,  H01L29/10

Abstract: Methods, systems, and devices for single-crystal transistors for memory devices are described. In some examples, a cavity may be formed through at least a portion of one or more dielectric materials, which may be deposited above a deck of memory cells. The cavity may include a taper, such as a taper toward a point, or a taper having an included angle that is within a range, or a taper from a cross-sectional area to some fraction of the cross-sectional area, among other examples. A semiconductor material may be deposited in the cavity and above the one or more dielectric materials, and formed in a single crystalline arrangement based on heating and cooling the deposited semiconductor material. One or more portions of a transistor, such as a channel portion of a transistor, may be formed at least in part by doping the single crystalline arrangement of the semiconductor material.

公开(公告)号：US11469103B2

公开(公告)日：2022-10-11

申请号：US17153997

申请日：2021-01-21

Applicant: Micron Technology, Inc.

Inventor： Nicholas R. Tapias ,  Sanjeev Sapra ,  Anish A. Khandekar ,  Shen Hu

IPC: H01L21/02 ,  H01L21/762 ,  H01L21/8238

Abstract: Methods, apparatuses, and systems related to semiconductor structure formation are described. An example method includes forming an opening through silicon (Si) material, formed over a semiconductor substrate, to a first depth to form pillars of Si material. The example method further includes depositing an isolation material within the opening to fill the opening between the Si pillars. The example method further includes removing a portion of the isolation material from between the pillars to a second depth to create a second opening between the pillars and defining inner sidewalls between the pillars. The example method further includes depositing an enhancer material over a top surface of the pillars and along the inner sidewalls of the pillars down to a top portion of the isolation material.

公开(公告)号：US20240105766A1

公开(公告)日：2024-03-28

申请号：US18531525

申请日：2023-12-06

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege ,  Masihhur R. Laskar ,  Nicholas R. Tapias ,  Darwin Franseda Fan ,  Manuj Nahar

IPC: H01L29/04 ,  H01L29/10

CPC classification number: H01L29/04 ,  H01L29/1033 ,  H10B12/00

Abstract: Methods, systems, and devices for single-crystal transistors for memory devices are described. In some examples, a cavity may be formed through at least a portion of one or more dielectric materials, which may be deposited above a deck of memory cells. The cavity may include a taper, such as a taper toward a point, or a taper having an included angle that is within a range, or a taper from a cross-sectional area to some fraction of the cross-sectional area, among other examples. A semiconductor material may be deposited in the cavity and above the one or more dielectric materials, and formed in a single crystalline arrangement based on heating and cooling the deposited semiconductor material. One or more portions of a transistor, such as a channel portion of a transistor, may be formed at least in part by doping the single crystalline arrangement of the semiconductor material.

公开(公告)号：US20220102351A1

公开(公告)日：2022-03-31

申请号：US17643316

申请日：2021-12-08

Applicant: Micron Technology, Inc.

Inventor： Song Guo ,  Sanh D. Tang ,  Shen Hu ,  Yan Li ,  Nicholas R. Tapias

IPC: H01L27/108 ,  G11C11/408

Abstract: A method of forming an apparatus comprises forming pillar structures extending from a base material. Upper portions of the pillar structures may exhibit a lateral width that is relatively greater than a lateral width of lower portions of the pillar structures. The method also comprises forming access lines laterally adjacent to the lower portions of the pillar structures and forming digit lines above upper surfaces of the pillar structures. Memory devices and electronic systems are also described.

公开(公告)号：US20210143011A1

公开(公告)日：2021-05-13

申请号：US17153997

申请日：2021-01-21

Applicant: Micron Technology, Inc.

Inventor： Nicholas R. Tapias ,  Sanjeev Sapra ,  Anish A. Khandekar ,  Shen Hu

IPC: H01L21/02 ,  H01L21/762

Abstract: Methods, apparatuses, and systems related to semiconductor structure formation are described. An example method includes forming an opening through silicon (Si) material, formed over a semiconductor substrate, to a first depth to form pillars of Si material. The example method further includes depositing an isolation material within the opening to fill the opening between the Si pillars. The example method further includes removing a portion of the isolation material from between the pillars to a second depth to create a second opening between the pillars and defining inner sidewalls between the pillars. The example method further includes depositing an enhancer material over a top surface of the pillars and along the inner sidewalls of the pillars down to a top portion of the isolation material.

公开(公告)号：US20210202487A1

公开(公告)日：2021-07-01

申请号：US16729076

申请日：2019-12-27

Applicant: Micron Technology, Inc.

Inventor： Song Guo ,  Sanh D. Tang ,  Shen Hu ,  Yan Li ,  Nicholas R. Tapias

IPC: H01L27/108 ,  G11C11/408

Abstract: A method of forming an apparatus comprises forming pillar structures extending from a base material. Upper portions of the pillar structures may exhibit a lateral width that is relatively greater than a lateral width of lower portions of the pillar structures. The method also comprises forming access lines laterally adjacent to the lower portions of the pillar structures and forming digit lines above upper surfaces of the pillar structures. Memory devices and electronic systems are also described.

公开(公告)号：US10978295B2

公开(公告)日：2021-04-13

申请号：US16445507

申请日：2019-06-19

Applicant: Micron Technology, Inc.

Inventor： Guangjun Yang ,  Nicholas R. Tapias

IPC: H01L27/105 ,  H01L27/22 ,  H01L21/02 ,  G11C5/06 ,  H01L27/24

Abstract: Systems, apparatuses, and methods related to epitaxial growth on semiconductor structures are described. An apparatus may include a working surface of a substrate material and a storage node connected to an active area of an access device on the working surface. The apparatus may also include a material epitaxially grown over the storage node contact to enclose a non-solid space between the storage node contact and passing sense lines.

公开(公告)号：US20200286895A1

公开(公告)日：2020-09-10

申请号：US16809924

申请日：2020-03-05

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  Srinivas Pulugurtha ,  Richard J. Hill ,  Yunfei Gao ,  Nicholas R. Tapias ,  Litao Yang ,  Haitao Liu

IPC: H01L27/108

Abstract: Some embodiments include an integrated assembly having digit lines which extend along a first direction, and which are spaced from one another by intervening regions. Each of the intervening regions has a first width along a cross-section. Pillars extend upwardly from the digit lines; and the pillars include transistor channel regions extending vertically between upper and lower source/drain regions. Storage elements are coupled with the upper source/drain regions. Wordlines extend along a second direction which crosses the first direction. The wordlines include gate regions adjacent the channel regions. Shield lines are within the intervening regions and extend along the first direction. The shield lines may be coupled with at least one reference voltage node. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20240274113A1

公开(公告)日：2024-08-15

申请号：US18417273

申请日：2024-01-19

Applicant: Micron Technology, Inc.

Inventor： Nicholas R. Tapias ,  Anthony J. Kanago

IPC: G10K11/178 ,  H04R1/10

CPC classification number: G10K11/17823 ,  G10K11/17827 ,  G10K11/17873 ,  H04R1/1041 ,  H04R1/1083 ,  G10K2210/1081 ,  G10K2210/30231 ,  G10K2210/3027 ,  G10K2210/3028 ,  G10K2210/3044 ,  H04R2420/07 ,  H04R2460/01

Abstract: Techniques, apparatuses, and systems for wireless communication between proximate devices are disclosed. A first microphone on a first wearable audio device of a first user receives first audio signals that include speech from a second user proximate to the first user and ambient noise from an environment surrounding the first wearable audio device. The first audio signals are analyzed to determine primary audio directed to the first user. The primary audio is compared to other audio signals received through wireless communication channels between the first wearable audio device and one or more other wearable audio devices. In doing so, some of the other audio signals are determined to be similar to the primary audio and are thus output to the first wearable audio device. As a result, two users can accurately communicate, even in a noisy environment.

公开(公告)号：US11805645B2

公开(公告)日：2023-10-31

申请号：US16542645

申请日：2019-08-16

Applicant: Micron Technology, Inc.

Inventor： Nicholas R. Tapias ,  Andrew Li ,  Adam W. Saxler ,  Kunal Shrotri ,  Erik R. Byers ,  Matthew J. King ,  Diem Thy N. Tran ,  Wei Yeeng Ng ,  Anish A. Khandekar

IPC: H10B43/27 ,  H01L21/02 ,  H01L21/285 ,  H10B41/27

CPC classification number: H10B43/27 ,  H01L21/0217 ,  H01L21/02164 ,  H01L21/02532 ,  H01L21/02631 ,  H01L21/02636 ,  H01L21/28568 ,  H10B41/27

Abstract: Some embodiments include a structure having an opening extending into an integrated configuration. A first material is within the opening, and is configured to create an undulating topography relative to a sidewall of the opening. The undulating topography has a surface roughness characterized by a mean roughness parameter Rmean which is the mean peak-to-valley distance along the undulating topography. The Rmean is at least about 4 nm. A second material is within the opening and along at least a portion of the undulating topography. The first and second materials are compositionally different from one another. Some embodiments include integrated assemblies. Some embodiments include methods of forming integrated assemblies.