公开(公告)号：US20210286525A1

公开(公告)日：2021-09-16

申请号：US17332468

申请日：2021-05-27

Applicant: Micron Technology, Inc.

Inventor： Kishore K. Muchherla ,  Ashutosh Malshe ,  Preston A. Thomson ,  Michael G. Miller ,  Sampath K. Ratnam ,  Renato C. Padilla ,  Peter Feeley

IPC: G06F3/06 ,  G11C16/10 ,  G11C16/16 ,  G11C16/34 ,  G11C11/56

Abstract: The present disclosure includes memory blocks erasable in a single level cell mode. A number of embodiments include a memory comprising a plurality of mixed mode blocks and a controller. The controller may be configured to identify a particular mixed mode block for an erase operation and, responsive to a determined intent to subsequently write the particular mixed mode block in a single level cell (SLC) mode, perform the erase operation in the SLC mode.

公开(公告)号：US10854299B2

公开(公告)日：2020-12-01

申请号：US15994151

申请日：2018-05-31

Applicant: Micron Technology, Inc.

Inventor： Kevin R. Brandt ,  Adam J. Hieb ,  Jonathan Tanguy ,  Preston A. Thomson

IPC: G11C7/00 ,  G11C16/16 ,  G11C16/08 ,  G11C7/20

Abstract: A data erase operation is performed on the memory system. The directed data erase operation performed on the memory system erases blocks of the memory device including blocks that are indicated as not including user data. In some embodiments, a data erase operation may be performed on a memory system to erase those groups of memory cells (e.g., blocks) indicated as not including user data. In some embodiments, a data erase operation may be performed on a memory system to erase those groups of memory cells (e.g., blocks) indicated as valid without erasing those groups of memory cells (e.g., blocks) indicated as invalid. In some embodiments, a data erase operation that can be performed on a memory system may obtain information associated with failing scenes of groups of memory cells (e.g., blocks) prior to obtaining the information, and erase the blocks (e.g., invalid blocks) subsequently.

公开(公告)号：US20190278490A1

公开(公告)日：2019-09-12

申请号：US16420505

申请日：2019-05-23

Applicant: Micron Technology, Inc.

Inventor： Kishore K. Muchherla ,  Ashutosh Malshe ,  Preston A. Thomson ,  Michael G. Miller ,  Sampath K. Ratnam ,  Renato C. Padilla ,  Peter Feeley

IPC: G06F3/06 ,  G11C11/56 ,  G11C16/34 ,  G11C16/16 ,  G11C16/10

Abstract: The present disclosure includes memory blocks erasable in a single level cell mode. A number of embodiments include a memory comprising a plurality of mixed mode blocks and a controller. The controller may be configured to identify a particular mixed mode block for an erase operation and, responsive to a determined intent to subsequently write the particular mixed mode block in a single level cell (SLC) mode, perform the erase operation in the SLC mode.

公开(公告)号：US10325668B2

公开(公告)日：2019-06-18

申请号：US15479356

申请日：2017-04-05

Applicant: Micron Technology, Inc.

Inventor： Kishore K. Muchherla ,  Ashutosh Malshe ,  Preston A. Thomson ,  Michael G. Miller ,  Gary F. Besinga ,  Scott A. Stoller ,  Sampath K. Ratnam ,  Renato C. Padilla ,  Peter Feeley

IPC: G11C16/34

Abstract: Apparatuses and methods for operating mixed mode blocks. One example method can include tracking single level cell (SLC) mode cycles and extra level cell (XLC) mode cycles performed on the mixed mode blocks, maintaining a mixed mode cycle count corresponding to the mixed mode blocks, and adjusting the mixed mode cycle count differently for mixed mode blocks operated in a SLC mode than for mixed blocks operated in a XLC mode.