公开(公告)号：US20130124830A1

公开(公告)日：2013-05-16

申请号：US13730841

申请日：2012-12-29

Applicant: Alexander Peleg ,  Yaakov Yaari ,  Millind Mittal ,  Larry M. Mennemeier ,  Benney Eitan

Inventor： Alexander Peleg ,  Yaakov Yaari ,  Millind Mittal ,  Larry M. Mennemeier ,  Benney Eitan

IPC: G06F9/30

CPC classification number: G06F9/30036 ,  G06F7/49921 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/30109 ,  G06F9/3013 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/30167 ,  G06F9/30181 ,  G06F9/30192 ,  G06F9/30196

Abstract: An apparatus includes an instruction decoder, first and second source registers and a circuit coupled to the decoder to receive packed data from the source registers and to unpack the packed data responsive to an unpack instruction received by the decoder. A first packed data element and a third packed data element are received from the first source register. A second packed data element and a fourth packed data element are received from the second source register. The circuit copies the packed data elements into a destination register resulting with the second packed data element adjacent to the first packed data element, the third packed data element adjacent to the second packed data element, and the fourth packed data element adjacent to the third packed data element.

Abstract translation: 一种装置包括指令解码器，第一和第二源寄存器以及耦合到解码器的电路，用于从源寄存器接收压缩数据，并根据解码器接收到的解包指令对打包数据进行解包。 从第一源寄存器接收第一打包数据元素和第三打包数据元素。 从第二源寄存器接收第二打包数据元素和第四打包数据元素。 所述电路将打包的数据元素复制到目的地寄存器中，其中与第一打包数据元素相邻的第二打包数据元素，与第二打包数据元素相邻的第三打包数据元素以及与第三打包数据元素相邻的第四打包数据元素 数据元素。

公开(公告)号：US20130117547A1

公开(公告)日：2013-05-09

申请号：US13730837

申请日：2012-12-29

Applicant: Alexander Peleg ,  Yaakov Yaari ,  Millind Mittal ,  Larry M. Mennemeier ,  Benny Eitan

Inventor： Alexander Peleg ,  Yaakov Yaari ,  Millind Mittal ,  Larry M. Mennemeier ,  Benny Eitan

IPC: G06F9/30

CPC classification number: G06F9/30036 ,  G06F7/49921 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/30109 ,  G06F9/3013 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/30167 ,  G06F9/30181 ,  G06F9/30192 ,  G06F9/30196

Abstract: An apparatus includes an instruction decoder, first and second source registers and a circuit coupled to the decoder to receive packed data from the source registers and to unpack the packed data responsive to an unpack instruction received by the decoder. A first packed data element and a third packed data element are received from the first source register. A second packed data element and a fourth packed data element are received from the second source register. The circuit copies the packed data elements into a destination register resulting with the second packed data element adjacent to the first packed data element, the third packed data element adjacent to the second packed data element, and the fourth packed data element adjacent to the third packed data element.

Abstract translation: 一种装置包括指令解码器，第一和第二源寄存器以及耦合到解码器的电路，用于从源寄存器接收压缩数据，并根据解码器接收到的解包指令对打包数据进行解包。 从第一源寄存器接收第一打包数据元素和第三打包数据元素。 从第二源寄存器接收第二打包数据元素和第四打包数据元素。 所述电路将打包的数据元素复制到目的地寄存器中，其中与第一打包数据元素相邻的第二打包数据元素，与第二打包数据元素相邻的第三打包数据元素以及与第三打包数据元素相邻的第四打包数据元素 数据元素。

公开(公告)号：US20120008755A1

公开(公告)日：2012-01-12

申请号：US12951018

申请日：2010-11-20

Applicant: Millind Mittal

Inventor： Millind Mittal

IPC: H04M11/00 ,  G06F3/048 ,  H04M15/06

CPC classification number: H04M3/493 ,  H04M3/4931 ,  H04M15/06 ,  H04M2203/254

Abstract: Method of using a computerized smart phone to navigate remote auto attendant telephony systems with a menu structure. The auto attendant's menu structure is put into an online computer database. When the caller uses the smart phone to call and establish a voice channel with remote auto attendant telephony system (using the telephone number of that system), software applications running on the caller's smart phone communication device intercept the telephone number and along with the voice channel, also establish a data channel with the online computer accessible database. The caller's smart phone can then retrieve at least some of the menu structure of the auto attendant telephony system through this data channel. This application software can then display at least some of the menu structure of the remote auto attendant telephony system on the graphical user interface of the user's smart phone synchronized with the audio delivery of the menu structure, facilitating interactions with the auto attendant system.

Abstract translation: 使用计算机智能手机导航具有菜单结构的远程自动话务员电话系统的方法。 自动助理的菜单结构放在一个在线计算机数据库中。 当呼叫者使用智能电话与远程自动话务员电话系统（使用该系统的电话号码）呼叫并建立语音信道时，在呼叫者的智能电话通信设备上运行的软件应用程序拦截电话号码以及语音信道 ，也建立与在线计算机可访问数据库的数据通道。 呼叫者的智能手机可以通过该数据信道来检索自动话务员电话系统的至少一些菜单结构。 该应用软件然后可以在与菜单结构的音频传送同步的用户智能电话的图形用户界面上显示远程自动话务员电话系统的至少一些菜单结构，从而促进与自动助理系统的交互。

公开(公告)号：US20110219214A1

公开(公告)日：2011-09-08

申请号：US13108723

申请日：2011-05-16

Applicant: Alexander Peleg ,  Yaakov Yaari ,  Millind Mittal ,  Larry M. Mennemeier ,  Benny Eitan

Inventor： Alexander Peleg ,  Yaakov Yaari ,  Millind Mittal ,  Larry M. Mennemeier ,  Benny Eitan

IPC: G06F9/30

CPC classification number: G06F9/30036 ,  G06F7/49921 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/30109 ,  G06F9/3013 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/30167 ,  G06F9/30181 ,  G06F9/30192 ,  G06F9/30196

Abstract: A processor. The processor includes a first register for storing a first packed data, a decoder, and a functional unit. The decoder has a control signal input. The control signal input is for receiving a first control signal and a second control signal. The first control signal is for indicating a pack operation. The second control signal is for indicating an unpack operation. The functional unit is coupled to the decoder and the register. The functional unit is for performing the pack operation and the unpack operation using the first packed data. The processor also supports a move operation.

Abstract translation: 处理器 处理器包括用于存储第一打包数据的第一寄存器，解码器和功能单元。 解码器具有控制信号输入。 控制信号输入用于接收第一控制信号和第二控制信号。 第一控制信号用于指示包装操作。 第二控制信号用于指示解封装操作。 功能单元耦合到解码器和寄存器。 功能单元用于使用第一打包数据执行包操作和拆包操作。 处理器还支持移动操作。

公开(公告)号：US07395298B2

公开(公告)日：2008-07-01

申请号：US10611621

申请日：2003-06-30

Applicant: Eric Debes ,  William W. Macy ,  Jonathan J. Tyler ,  Alexander D. Peleg ,  Millind Mittal ,  Larry M. Mennemeier ,  Benny Eitan ,  Carole Dulong ,  Eiichi Kowashi ,  Wolf Witt

Inventor： Eric Debes ,  William W. Macy ,  Jonathan J. Tyler ,  Alexander D. Peleg ,  Millind Mittal ,  Larry M. Mennemeier ,  Benny Eitan ,  Carole Dulong ,  Eiichi Kowashi ,  Wolf Witt

IPC: G06F7/38

CPC classification number: G06F7/5324 ,  G06F7/4812 ,  G06F7/49921 ,  G06F7/5338 ,  G06F7/5443 ,  G06F9/30014 ,  G06F9/30018 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/3885 ,  G06F15/7857 ,  G06F17/147 ,  G06F17/16 ,  G06F2207/3828 ,  G06T1/20

Abstract: A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least two of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed data.

Abstract translation: 一种用于在处理器中包括用于对压缩数据进行乘法运算的指令的方法和装置。 在一个实施例中，处理器耦合到存储器。 存储器中存储有第一打包数据和第二打包数据。 处理器对所述第一打包数据和所述第二打包数据中的数据元素执行操作，以响应于接收到指令而产生第三打包数据。 该第三打包数据中的至少两个数据元素存储对第一和第二打包数据中的数据元素执行加法运算的结果。

公开(公告)号：US07380278B2

公开(公告)日：2008-05-27

申请号：US11386269

申请日：2006-03-21

Applicant: Carl M. Ellison ,  Roger A. Golliver ,  Howard C. Herbert ,  Derrick C. Lin ,  Francis X. McKeen ,  Gilbert Neiger ,  Ken Reneris ,  James A. Sutton ,  Shreekant S. Thakkar ,  Millind Mittal

Inventor： Carl M. Ellison ,  Roger A. Golliver ,  Howard C. Herbert ,  Derrick C. Lin ,  Francis X. McKeen ,  Gilbert Neiger ,  Ken Reneris ,  James A. Sutton ,  Shreekant S. Thakkar ,  Millind Mittal

IPC: G06F7/04 ,  G06F9/00 ,  G06F12/00 ,  H04L9/00 ,  H04L9/32

CPC classification number: G06F21/53 ,  G06F9/468 ,  G06F21/562 ,  G06F21/57 ,  G06F21/74 ,  G06F2221/2105

Abstract: A processing system has a processor that can operate in a normal ring 0 operating mode and one or more higher ring operating modes above the normal ring 0 operating mode. In addition, the processor can operate in an isolated execution mode. A memory in the processing system may include an ordinary memory area that can be accessed from the normal ring 0 operating mode, as well as an isolated memory area that can be accessed from the isolated execution mode but not from the normal ring 0 operating mode. The processing system may also include an operating system (OS) nub, as well as a key generator. The key generator may generate an OS nub key (OSNK) based at least in part on an identification of the OS nub and a master binding key (BK0) of the platform. Other embodiments are described and claimed.

Abstract translation: 处理系统具有处理器，该处理器可以在正常环0操作模式和高于正常环0操作模式的一个或多个较高环操作模式下操作。 此外，处理器可以在隔离的执行模式下操作。 处理系统中的存储器可以包括可以从正常环0操作模式访问的普通存储器区域以及可以从隔离执行模式而不是从正常环0操作模式访问的隔离存储器区域。 处理系统还可以包括操作系统（OS）nub以及密钥生成器。 密钥生成器可以至少部分地基于OS nub的标识和平台的主绑定密钥（BK 0）来生成OS nub密钥（OSNK）。 描述和要求保护其他实施例。

公开(公告)号：US20080022073A1

公开(公告)日：2008-01-24

申请号：US11888411

申请日：2007-07-31

Applicant: Millind Mittal ,  Mehul Kharidia ,  Tarun Tripathy ,  J. Mertoguno

Inventor： Millind Mittal ,  Mehul Kharidia ,  Tarun Tripathy ,  J. Mertoguno

IPC: G06F9/30

CPC classification number: H04L29/06 ,  H04L69/10 ,  H04L69/16 ,  H04L69/161 ,  H04L69/165

Abstract: A functional-level instruction-set computing (FLIC) architecture executes higher-level functional instructions such as lookups and bit-compares of variable-length operands. Each FLIC processing-engine slice has specialized processing units including a lookup unit that searches for a matching entry in a lookup cache. Variable-length operands are stored in execution buffers. The operand length and location in the execution buffer are stored in fixed-length general-purpose registers (GPRs) that also store fixed-length operands. A copy/move unit moves data between input and output buffers and one or more FLIC processing-engine slices. Multiple contexts can each have a set of GPRs and execution buffers. An expansion buffer in a FLIC slice can be allocated to a context to expand that context's execution buffer for storing longer operands. The FLIC engine is optimized to parse, lookup, and process long strings common in content-service requests and can offload file-server requests by looking up meta-data and pointers.

Abstract translation: 功能级指令集计算（FLIC）架构执行诸如可变长度操作数的查找和比特比较的更高级功能指令。 每个FLIC处理引擎切片具有专门的处理单元，其包括查找单元，其在查找高速缓存中搜索匹配的条目。 可变长度操作数存储在执行缓冲区中。 执行缓冲区中的操作数长度和位置存储在也存储固定长度操作数的固定长度通用寄存器（GPR）中。 复制/移动单元在输入和输出缓冲器和一个或多个FLIC处理引擎切片之间移动数据。 多个上下文可以各自具有一组GPR和执行缓冲区。 可以将FLIC切片中的扩展缓冲区分配给上下文，以扩展该上下文的执行缓冲区以存储较长的操作数。 FLIC引擎经过优化，可解析，查找和处理内容服务请求中常见的长字符串，并可通过查找元数据和指针来卸载文件服务器请求。

公开(公告)号：US20070239810A1

公开(公告)日：2007-10-11

申请号：US11758767

申请日：2007-06-06

Applicant: DERRICK LIN ,  Punit Minocha ,  Alexander Peleg ,  Yaakov Yaari ,  Millind Mittal ,  Larry Mennemeier ,  Benny Eitan

Inventor： DERRICK LIN ,  Punit Minocha ,  Alexander Peleg ,  Yaakov Yaari ,  Millind Mittal ,  Larry Mennemeier ,  Benny Eitan

IPC: G06F17/00

CPC classification number: G06F7/762 ,  G06F5/01 ,  G06F7/49994 ,  G06F7/76 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30109 ,  G06F9/3013 ,  G06F9/30167 ,  G06F9/3885

Abstract: A method and apparatus for providing, in a processor, a shift operation on a packed data element having multiple values. One embodiment of a central processing unit (CPU) includes instruction fetch logic to fetch a single-instruction-multiple-data (SIMD) shift instruction. A register stores a multiple data elements to be operated upon by the SIMD shift instruction. A barrel shifter concurrently shifts the data elements in a bit-wise manner by a variable number of bit positions in response to the SIMD shift instruction.

Abstract translation: 一种用于在处理器中提供对具有多个值的压缩数据元素进行移位操作的方法和装置。 中央处理单元（CPU）的一个实施例包括提取单指令多数据（SIMD）移位指令的指令提取逻辑。 寄存器存储通过SIMD移位指令来操作的多个数据元素。 桶形移位器响应于SIMD移位指令，同时将数据元素按比特方式移位可变数目的位位置。

公开(公告)号：US20060236076A1

公开(公告)日：2006-10-19

申请号：US11451906

申请日：2006-06-12

Applicant: Alexander Peleg ,  Yaakov Yaari ,  Millind Mittal ,  Larry Mennemeier ,  Benny Eitan

Inventor： Alexander Peleg ,  Yaakov Yaari ,  Millind Mittal ,  Larry Mennemeier ,  Benny Eitan

IPC: G06F15/00

CPC classification number: G06F9/30036 ,  G06F7/49921 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/30109 ,  G06F9/3013 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/30167 ,  G06F9/30181 ,  G06F9/30192 ,  G06F9/30196

Abstract: An apparatus includes an instruction decoder, first and second source registers and a circuit coupled to the decoder to receive packed data from the source registers and to pack the packed data responsive to a pack instruction received by the decoder. A first packed data element and a second packed data element are received from the first source register. A third packed data element and a fourth packed data element are received from the second source register. The circuit packs packing a portion of each of the packed data elements into a destination register resulting with the portion from second packed data element adjacent to the portion from the first packed data element, and the portion from the fourth packed data element adjacent to the portion from the third packed data element.

公开(公告)号：US20060235914A1

公开(公告)日：2006-10-19

申请号：US11454749

申请日：2006-06-15

Applicant: Derrick Lin ,  Punit Minocha ,  Alexander Peleg ,  Yaakov Yaari ,  Millind Mittal ,  Larry Mennemeier ,  Benny Eitan

Inventor： Derrick Lin ,  Punit Minocha ,  Alexander Peleg ,  Yaakov Yaari ,  Millind Mittal ,  Larry Mennemeier ,  Benny Eitan

IPC: G06F15/00

CPC classification number: G06F7/762 ,  G06F5/01 ,  G06F7/49994 ,  G06F7/76 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30109 ,  G06F9/3013 ,  G06F9/30167 ,  G06F9/3885

Abstract: A method and apparatus for providing, in a processor, a shift operation on a packed data element having multiple values. The apparatus having multiple muxes, each of the multiple muxes having a first input, a second input, a select input and an output. Each of the multiple bits that represent a shifted packed intermediate result on a first bus is coupled to the corresponding first input. Each of the multiple bits representing a replacement bit for one of the multiple values is coupled to a corresponding second input. Each of the multiple bits driven by a correction circuit is coupled to a corresponding select input. Each output corresponds to a bit of a shifted packed result.

Abstract translation: 一种用于在处理器中提供对具有多个值的压缩数据元素进行移位操作的方法和装置。 所述装置具有多个多路复用器，所述多个多路复用器中的每一个具有第一输入，第二输入，选择输入和输出。 表示在第一总线上的移位的打包中间结果的多个比特中的每一个被耦合到对应的第一输入。 表示多个值之一的替换位的多个比特中的每一个被耦合到对应的第二输入。 由校正电路驱动的多个比特中的每一个被耦合到对应的选择输入。 每个输出对应于移位包装结果的一位。