公开(公告)号：US20060206943A1

公开(公告)日：2006-09-14

申请号：US11386269

申请日：2006-03-21

Applicant: Carl Ellison ,  Roger Golliver ,  Howard Herbert ,  Derrick Lin ,  Francis McKeen ,  Gilbert Neiger ,  Ken Reneris ,  James Sutton ,  Shreekant Thakkar ,  Millind Mittal

Inventor： Carl Ellison ,  Roger Golliver ,  Howard Herbert ,  Derrick Lin ,  Francis McKeen ,  Gilbert Neiger ,  Ken Reneris ,  James Sutton ,  Shreekant Thakkar ,  Millind Mittal

IPC: H04N7/16

CPC classification number: G06F21/53 ,  G06F9/468 ,  G06F21/562 ,  G06F21/57 ,  G06F21/74 ,  G06F2221/2105

Abstract: A processing system has a processor that can operate in a normal ring 0 operating mode and one or more higher ring operating modes above the normal ring 0 operating mode. In addition, the processor can operate in an isolated execution mode. A memory in the processing system may include an ordinary memory area that can be accessed from the normal ring 0 operating mode, as well as an isolated memory area that can be accessed from the isolated execution mode but not from the normal ring 0 operating mode. The processing system may also include an operating system (OS) nub, as well as a key generator. The key generator may generate an OS nub key (OSNK) based at least in part on an identification of the OS nub and a master binding key (BK0) of the platform. Other embodiments are described and claimed.

Abstract translation: 处理系统具有处理器，该处理器可以在正常环0操作模式和高于正常环0操作模式的一个或多个较高环操作模式下操作。 此外，处理器可以在隔离的执行模式下操作。 处理系统中的存储器可以包括可以从正常环0操作模式访问的普通存储器区域以及可以从隔离执行模式而不是从正常环0操作模式访问的隔离存储器区域。 处理系统还可以包括操作系统（OS）nub以及密钥生成器。 密钥生成器可以至少部分地基于OS nub的标识和平台的主绑定密钥（BK 0）来生成OS nub密钥（OSNK）。 描述和要求保护其他实施例。

公开(公告)号：US20050038977A1

公开(公告)日：2005-02-17

申请号：US10940268

申请日：2004-09-13

Applicant: Andrew Glew ,  Larry Mennemeier ,  Alexander Peleg ,  David Bistry ,  Millind Mittal ,  Carole Dulong ,  Eiichi Kowashi ,  Benny Eitan ,  Derrick Lin ,  Ramamohan Vakkalagadda

Inventor： Andrew Glew ,  Larry Mennemeier ,  Alexander Peleg ,  David Bistry ,  Millind Mittal ,  Carole Dulong ,  Eiichi Kowashi ,  Benny Eitan ,  Derrick Lin ,  Ramamohan Vakkalagadda

IPC: G06F9/30 ,  G06F9/318 ,  G06F9/455 ,  G06F9/46

CPC classification number: G06F9/3017 ,  G06F9/30036 ,  G06F9/30105 ,  G06F9/30109 ,  G06F9/30112 ,  G06F9/30134 ,  G06F9/30189 ,  G06F9/384 ,  G06F9/462

Abstract: A processor with instructions to operate on different data types stored in a single logical register file. According to one embodiment of the invention, a processor includes a number of physical registers, a memory unit, and a decode/execution unit. The memory unit is to make the number of physical registers appear to software as a single software-visible register file. The decode/execution unit is to execute on the contents of the single software-visible register file instructions of a first instruction type and of a second instruction type, wherein the single software-visible register file is to be operated as a flat register file during execution of instructions of the second instruction type and as a stack referenced register file during execution of instructions of the first instruction type.

Abstract translation: 具有对存储在单个逻辑寄存器文件中的不同数据类型进行操作的指令的处理器。 根据本发明的一个实施例，处理器包括多个物理寄存器，存储器单元和解码/执行单元。 存储单元是将物理寄存器的数量作为单个软件可见的寄存器文件显示在软件上。 解码/执行单元执行第一指令类型和第二指令类型的单个软件可见寄存器文件指令的内容，其中单个软件可见寄存器文件将作为平坦寄存器文件操作 在执行第一指令类型的指令期间执行第二指令类型的指令和作为堆栈引用的寄存器堆栈。

公开(公告)号：US06631452B1

公开(公告)日：2003-10-07

申请号：US09561145

申请日：2000-04-28

Applicant: Derrick Lin

Inventor： Derrick Lin

IPC: G06F1300

CPC classification number: G06F9/3824 ,  G06F9/30043 ,  G06F9/30076 ,  G06F9/30127 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3842

Abstract: A computer system is provided having a register stack engine to manage data transfers between a backing store and a register stack. The computer system includes a processor and a memory coupled to the processor through a memory channel. The processor includes a register stack to store data from one or more procedures in one or more frames, respectively. The register stack engine monitors activity on the memory channel and transfers data between selected frames of the register stack and a backing store in the memory responsive to the available bandwidth on the memory channel.

Abstract translation: 提供了一种计算机系统，其具有用于管理后备存储器和寄存器堆栈之间的数据传输的寄存器堆栈引擎。 计算机系统包括处理器和通过存储器通道耦合到处理器的存储器。 处理器包括分别在一个或多个帧中存储来自一个或多个过程的数据的寄存器堆栈。 寄存器堆栈引擎监视存储器通道上的活动，并且响应于存储器通道上的可用带宽，在寄存器堆栈的选定帧和存储器之间传送数据。

公开(公告)号：US20050188198A1

公开(公告)日：2005-08-25

申请号：US11115829

申请日：2005-04-26

Applicant: Carl Ellison ,  Roger Golliver ,  Howard Herbert ,  Derrick Lin ,  Francis McKeen ,  Gilbert Neiger ,  Ken Reneris ,  James Sutton ,  Shreekant Thakkar ,  Millind Mittal

Inventor： Carl Ellison ,  Roger Golliver ,  Howard Herbert ,  Derrick Lin ,  Francis McKeen ,  Gilbert Neiger ,  Ken Reneris ,  James Sutton ,  Shreekant Thakkar ,  Millind Mittal

IPC: G06F12/14 ,  G06F15/00 ,  G06F21/00 ,  H04L9/00

CPC classification number: G06F12/1491 ,  G06F21/57 ,  G06F21/74

Abstract: An example processing system comprises a processor to execute in an isolated execution mode in a ring 0 operating mode. The processor also supports one or more higher ring operating modes, as well as a normal execution mode. The processing system also comprises memory, as well as a machine-accessible medium having instructions. When the processing system executes the instructions, the processing system configures the processor to run in the isolated execution mode, configures the processing system to establish an isolated memory area in the memory, and loads initialization software into the isolated memory area. The processing system may provide a manifest that represents the initialization software. The initialization software may be verified, based at least in part on the manifest.

Abstract translation: 示例处理系统包括处理器，其以环0操作模式以孤立执行模式执行。 处理器还支持一个或多个较高环操作模式以及正常执行模式。 处理系统还包括存储器以及具有指令的机器可访问介质。 当处理系统执行指令时，处理系统将处理器配置为以隔离执行模式运行，配置处理系统以在存储器中建立隔离的存储器区域，并将初始化软件加载到隔离存储器区域中。 处理系统可以提供表示初始化软件的清单。 至少部分地基于清单来验证初始化软件。

公开(公告)号：US20060200680A1

公开(公告)日：2006-09-07

申请号：US09672602

申请日：2001-02-26

Applicant: Carl Ellison ,  Roger Golliver ,  Howard Herbert ,  Derrick Lin ,  Francis McKeen ,  Gilbert Neiger ,  Ken Reneris ,  James Sutton ,  Shreekant Thakkar ,  Millind Mittal

Inventor： Carl Ellison ,  Roger Golliver ,  Howard Herbert ,  Derrick Lin ,  Francis McKeen ,  Gilbert Neiger ,  Ken Reneris ,  James Sutton ,  Shreekant Thakkar ,  Millind Mittal

IPC: G06F12/14

CPC classification number: G06F12/1491 ,  G06F21/57 ,  G06F2221/2105

Abstract: In an embodiment of the present invention, a technique is provided for remote attestation. An interface maps a device via a bus to an address space of a chipset in a secure environment for an isolated execution mode. The secure environment is associated with an isolated memory area accessible by at least one processor. The at least one processor operates in one of a normal execution mode and the isolated execution mode. A communication storage corresponding to the address space allows the device to exchange security information with the at least one processor in the isolated execution mode in a remote attestation.

Abstract translation: 在本发明的实施例中，提供了用于远程证明的技术。 接口将设备通过总线映射到安全环境中的芯片组的地址空间，用于隔离执行模式。 安全环境与由至少一个处理器可访问的隔离存储器区域相关联。 所述至少一个处理器以正常执行模式和隔离执行模式之一进行操作。 对应于地址空间的通信存储器允许设备在远程证明中以隔离执行模式与至少一个处理器交换安全信息。

公开(公告)号：US20060015719A1

公开(公告)日：2006-01-19

申请号：US11203538

申请日：2005-08-12

Applicant: Howard Herbert ,  David Grawrock ,  Carl Ellison ,  Roger Golliver ,  Derrick Lin ,  Francis McKeen ,  Gilbert Neiger ,  Ken Reneris ,  James Sutton ,  Shreekant Thakkar ,  Millind Mittal

Inventor： Howard Herbert ,  David Grawrock ,  Carl Ellison ,  Roger Golliver ,  Derrick Lin ,  Francis McKeen ,  Gilbert Neiger ,  Ken Reneris ,  James Sutton ,  Shreekant Thakkar ,  Millind Mittal

IPC: H04L9/00

CPC classification number: G06F21/305 ,  G06F9/30189 ,  G06F12/1491 ,  G06F21/35 ,  G06F21/53 ,  G06F21/57 ,  G06F21/575 ,  G06F21/64 ,  G06F21/74 ,  G06F2221/2101 ,  G06F2221/2103 ,  G06F2221/2105 ,  G06F2221/2149

Abstract: In one embodiment, a method of remote attestation for a special mode of operation. The method comprises storing an audit log within protected memory of a platform. The audit log is a listing of data representing each of a plurality of IsoX software modules loaded into the platform. The audit log is retrieved from the protected memory in response to receiving a remote attestation request from a remotely located platform. Then, the retrieved audit log is digitally signed to produce a digital signature for transfer to the remotely located platform.

公开(公告)号：US5852726A

公开(公告)日：1998-12-22

申请号：US574719

申请日：1995-12-19

Applicant: Derrick Lin ,  Romamohan R. Vakkalagadda ,  Andrew F. Glew ,  Larry M. Mennemeier ,  Alexander D. Peleg ,  David Bistry ,  Millind Mittal ,  Carole Dulong ,  Eiichi Kowashi ,  Benny Eitan

Inventor： Derrick Lin ,  Romamohan R. Vakkalagadda ,  Andrew F. Glew ,  Larry M. Mennemeier ,  Alexander D. Peleg ,  David Bistry ,  Millind Mittal ,  Carole Dulong ,  Eiichi Kowashi ,  Benny Eitan

IPC: G06F7/00 ,  G06F9/30 ,  G06F9/305 ,  G06F9/34 ,  G06F9/38 ,  G06F9/455 ,  G06F9/46 ,  G06F9/48 ,  G06F9/00

CPC classification number: G06F9/30123 ,  G06F9/30036 ,  G06F9/30109 ,  G06F9/30134 ,  G06F9/3824 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857

Abstract: A method and apparatus for executing floating point and packed data instructions using a single physical register file that is aliased. According to one aspect of the invention, a processor is provided that includes a decode unit, a mapping unit, and a storage unit. The decode unit is configured to decode instructions and their operands from at least one instruction set including at least a first and second set of instructions. The storage unit includes a physical register file. The mapping unit is configured to map operands used by the first set of instructions to the physical register file in a stack referenced manner. In addition, the mapping unit is configured to map operands used by the second set of instructions to the same physical register file in a non-stack reference manner.

Abstract translation: 一种用于使用别名的单个物理寄存器文件执行浮点和打包数据指令的方法和装置。 根据本发明的一个方面，提供一种包括解码单元，映射单元和存储单元的处理器。 解码单元被配置为从包括至少第一和第二组指令的至少一个指令集解码指令及其操作数。 存储单元包括物理寄存器文件。 映射单元被配置为以堆栈引用的方式将由第一组指令使用的操作数映射到物理寄存器文件。 此外，映射单元被配置为将第二组指令使用的操作数以非堆栈参考方式映射到相同的物理寄存器文件。

公开(公告)号：US5835748A

公开(公告)日：1998-11-10

申请号：US575704

申请日：1995-12-19

Applicant: Doron Orenstein ,  Ofri Wechsler ,  Millind Mittal ,  Andrew F. Glew ,  Larry M. Mennemeier ,  Alexander D. Peleg ,  David Bistry ,  Carole Dulong ,  Eiichi Kowashi ,  Benny Eitan ,  Derrick Lin ,  Ramamohan R. Vakkalagadda

Inventor： Doron Orenstein ,  Ofri Wechsler ,  Millind Mittal ,  Andrew F. Glew ,  Larry M. Mennemeier ,  Alexander D. Peleg ,  David Bistry ,  Carole Dulong ,  Eiichi Kowashi ,  Benny Eitan ,  Derrick Lin ,  Ramamohan R. Vakkalagadda

IPC: G06F9/30 ,  G06F9/302 ,  G06F9/318 ,  G06F9/38 ,  G06F9/00 ,  G06F9/06

CPC classification number: G06F9/30014 ,  G06F9/30036 ,  G06F9/30105 ,  G06F9/30109 ,  G06F9/3012 ,  G06F9/3013 ,  G06F9/30134 ,  G06F9/30192 ,  G06F9/3861

Abstract: A method and apparatus for executing different sets of instructions that cause a processor to perform different data type operations on different physical registers files that logically appear to software as a single aliased register file. According to one aspect of the invention, a processor is provided that includes at least two physical register files--one for executing scalar data type operations and the other for executing packed data type operations. In addition, the processor includes a transition unit that is configured to cause the two physical register files to logically appear to software executing on the processor as a single logical register file.

Abstract translation: 一种用于执行不同指令集的方法和装置，该方法和装置使处理器对不同的物理寄存器文件执行不同的数据类型操作，所述物理寄存器文件作为单个混叠寄存器文件逻辑上显示为软件。 根据本发明的一个方面，提供一种包括至少两个物理寄存器文件的处理器，一个用于执行标量数据类型操作，另一个用于执行打包数据类型操作。 另外，处理器还包括转移单元，其被配置为使两个物理寄存器文件逻辑地出现在处理器上执行的软件作为单个逻辑寄存器文件。

公开(公告)号：US20070239810A1

公开(公告)日：2007-10-11

申请号：US11758767

申请日：2007-06-06

Applicant: DERRICK LIN ,  Punit Minocha ,  Alexander Peleg ,  Yaakov Yaari ,  Millind Mittal ,  Larry Mennemeier ,  Benny Eitan

Inventor： DERRICK LIN ,  Punit Minocha ,  Alexander Peleg ,  Yaakov Yaari ,  Millind Mittal ,  Larry Mennemeier ,  Benny Eitan

IPC: G06F17/00

CPC classification number: G06F7/762 ,  G06F5/01 ,  G06F7/49994 ,  G06F7/76 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30109 ,  G06F9/3013 ,  G06F9/30167 ,  G06F9/3885

Abstract: A method and apparatus for providing, in a processor, a shift operation on a packed data element having multiple values. One embodiment of a central processing unit (CPU) includes instruction fetch logic to fetch a single-instruction-multiple-data (SIMD) shift instruction. A register stores a multiple data elements to be operated upon by the SIMD shift instruction. A barrel shifter concurrently shifts the data elements in a bit-wise manner by a variable number of bit positions in response to the SIMD shift instruction.

Abstract translation: 一种用于在处理器中提供对具有多个值的压缩数据元素进行移位操作的方法和装置。 中央处理单元（CPU）的一个实施例包括提取单指令多数据（SIMD）移位指令的指令提取逻辑。 寄存器存储通过SIMD移位指令来操作的多个数据元素。 桶形移位器响应于SIMD移位指令，同时将数据元素按比特方式移位可变数目的位位置。

公开(公告)号：US20060235914A1

公开(公告)日：2006-10-19

申请号：US11454749

申请日：2006-06-15

Applicant: Derrick Lin ,  Punit Minocha ,  Alexander Peleg ,  Yaakov Yaari ,  Millind Mittal ,  Larry Mennemeier ,  Benny Eitan

Inventor： Derrick Lin ,  Punit Minocha ,  Alexander Peleg ,  Yaakov Yaari ,  Millind Mittal ,  Larry Mennemeier ,  Benny Eitan

IPC: G06F15/00

CPC classification number: G06F7/762 ,  G06F5/01 ,  G06F7/49994 ,  G06F7/76 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30109 ,  G06F9/3013 ,  G06F9/30167 ,  G06F9/3885

Abstract: A method and apparatus for providing, in a processor, a shift operation on a packed data element having multiple values. The apparatus having multiple muxes, each of the multiple muxes having a first input, a second input, a select input and an output. Each of the multiple bits that represent a shifted packed intermediate result on a first bus is coupled to the corresponding first input. Each of the multiple bits representing a replacement bit for one of the multiple values is coupled to a corresponding second input. Each of the multiple bits driven by a correction circuit is coupled to a corresponding select input. Each output corresponds to a bit of a shifted packed result.

Abstract translation: 一种用于在处理器中提供对具有多个值的压缩数据元素进行移位操作的方法和装置。 所述装置具有多个多路复用器，所述多个多路复用器中的每一个具有第一输入，第二输入，选择输入和输出。 表示在第一总线上的移位的打包中间结果的多个比特中的每一个被耦合到对应的第一输入。 表示多个值之一的替换位的多个比特中的每一个被耦合到对应的第二输入。 由校正电路驱动的多个比特中的每一个被耦合到对应的选择输入。 每个输出对应于移位包装结果的一位。