公开(公告)号：US20200287027A1

公开(公告)日：2020-09-10

申请号：US16810492

申请日：2020-03-05

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Yasunari UMEMOTO ,  Isao OBU ,  Kaoru IDENO ,  Shigeki KOYA

IPC: H01L29/737 ,  H01L29/06 ,  H01L29/08

Abstract: A semiconductor device includes a collector layer, a base layer, and an emitter layer that are disposed above a substrate. An emitter mesa layer is disposed on a partial region of the emitter layer. In a plan view, the base electrode is disposed in or on a region which does not overlap the emitter mesa layer. The base electrode allows base current to flow to the base layer. In the plan view, a first edge forming part of edges of the emitter mesa layer extends in a first direction, and a second edge forming part of edges of the base electrode faces the first edge. A gap between the first edge and the second edge in a terminal portion located in an end portion of the emitter mesa layer in the first direction is wider than a gap in an intermediate portion of the emitter mesa layer.

公开(公告)号：US20200066886A1

公开(公告)日：2020-02-27

申请号：US16525400

申请日：2019-07-29

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Isao OBU ,  Yasunari UMEMOTO ,  Takayuki TSUTSUI ,  Satoshi TANAKA

IPC: H01L29/73 ,  H01L27/082 ,  H01L29/205 ,  H01L29/08 ,  H01L29/417 ,  H01L29/737 ,  H01L21/8252 ,  H01L21/285 ,  H01L21/306 ,  H01L21/308 ,  H01L29/66

Abstract: A first sub-collector layer functions as an inflow path of a collector current that flows in a collector layer of a heterojunction bipolar transistor. A collector ballast resistor layer having a lower doping concentration than the first sub-collector layer is disposed between the collector layer and the first sub-collector layer.

公开(公告)号：US20190198464A1

公开(公告)日：2019-06-27

申请号：US16223597

申请日：2018-12-18

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Takayuki TSUTSUI ,  Isao OBU

IPC: H01L23/66 ,  H01L27/06 ,  H01L23/528 ,  H01L23/00 ,  H01L49/02 ,  H01L29/737

CPC classification number: H01L23/66 ,  H01L23/5286 ,  H01L24/13 ,  H01L27/0658 ,  H01L28/10 ,  H01L28/40 ,  H01L29/7371 ,  H01L2223/6655 ,  H01L2224/13025 ,  H01L2224/13147 ,  H01L2924/30111 ,  H03F1/565 ,  H03F3/195 ,  H03F3/2178 ,  H03F2200/222 ,  H03F2200/387 ,  H03F2200/451 ,  H03H7/38

Abstract: A plurality of unit transistors that are connected in parallel to each other are formed on a substrate. In addition, a ground bump is provided on the substrate. A plurality of first capacitors are each provided for a corresponding one of the plurality of unit transistors and each connect an output electrode of the corresponding one of the plurality of unit transistors and the ground bump to each other.

公开(公告)号：US20190158044A1

公开(公告)日：2019-05-23

申请号：US16192890

申请日：2018-11-16

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Isao OBU ,  Satoshi TANAKA ,  Takayuki TSUTSUI ,  Yasunari UMEMOTO

IPC: H03F3/21 ,  H03F3/19 ,  H03F1/56 ,  H03F1/02 ,  H01L27/06

Abstract: A power amplifier includes initial-stage and output-stage amplifier circuits, and initial-stage and output-stage bias circuits. The initial-stage amplifier circuit includes a first high electron mobility transistor having a source electrically connected to a reference potential, and a gate to which a radio-frequency input signal is inputted, and a first heterojunction bipolar transistor having an emitter electrically connected to a drain of the first high electron mobility transistor, a base electrically connected to the reference potential in an alternate-current fashion, and a collector to which direct-current power is supplied and from which a radio-frequency signal is outputted. The output-stage amplifier circuit includes a second heterojunction bipolar transistor having an emitter electrically connected to the reference potential, a base to which the radio-frequency signal outputted from the first heterojunction bipolar transistor is inputted, and a collector to which direct-current power is supplied and from which a radio-frequency output signal is outputted.

公开(公告)号：US20180240766A1

公开(公告)日：2018-08-23

申请号：US15833098

申请日：2017-12-06

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Isao OBU ,  Yasunari Umemoto ,  Masahiro Shibata

IPC: H01L23/00 ,  H01L23/31 ,  H01L29/20

CPC classification number: H01L24/05 ,  H01L21/30617 ,  H01L21/3083 ,  H01L21/76898 ,  H01L23/3157 ,  H01L24/32 ,  H01L29/06 ,  H01L29/20 ,  H01L2224/0346 ,  H01L2224/04026 ,  H01L2224/05011 ,  H01L2224/05018 ,  H01L2224/05027 ,  H01L2224/05164 ,  H01L2224/05557 ,  H01L2224/05558 ,  H01L2224/05572 ,  H01L2224/05582 ,  H01L2224/05644 ,  H01L2224/26145 ,  H01L2224/29139 ,  H01L2224/29294 ,  H01L2224/29339 ,  H01L2224/32225 ,  H01L2924/10158 ,  H01L2924/1424 ,  H01L2924/35121 ,  H01L2924/00014

Abstract: A compound semiconductor substrate has a first main surface parallel to a first direction and a second direction perpendicular to the first direction, a second main surface located on a side opposite to the first main surface, and a recess. The recess has an opening, a bottom surface facing the opening, and a plurality of side surfaces located between the opening and the bottom surface. The side surfaces include at least one first side surface forming an angle of about θ degrees with the bottom surface in the recess and at least one second side surface forming an angle of about ϕ degrees with the bottom surface in the recess. The total length of edge lines between the first main surface and the at least one first side surface is larger than that of edge lines between the first main surface and the at least one second side surface.

公开(公告)号：US20170243939A1

公开(公告)日：2017-08-24

申请号：US15588859

申请日：2017-05-08

Applicant: MURATA MANUFACTURING CO., LTD.

Inventor： Isao OBU ,  Shigeru YOSHIDA

IPC: H01L29/10 ,  H01L29/205 ,  H03F1/56 ,  H01L27/082 ,  H03F3/21 ,  H01L29/737 ,  H01L29/73

CPC classification number: H01L29/1004 ,  H01L27/0823 ,  H01L27/1022 ,  H01L29/0692 ,  H01L29/0817 ,  H01L29/205 ,  H01L29/41708 ,  H01L29/66234 ,  H01L29/7304 ,  H01L29/732 ,  H01L29/7371 ,  H03F1/56 ,  H03F3/21 ,  H03F2200/222 ,  H03F2200/318 ,  H03F2200/387 ,  H03F2200/411

Abstract: A high-performance HBT that is unlikely to decrease the process controllability and to increase the manufacturing cost is implemented. A heterojunction bipolar transistor includes an emitter layer, a base layer, and a collector layer on a GaAs substrate. The emitter layer is formed of InGaP. The base layer is formed of GaAsPBi having a composition that substantially lattice-matches GaAs.

公开(公告)号：US20170236796A1

公开(公告)日：2017-08-17

申请号：US15587421

申请日：2017-05-05

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Isao OBU ,  Shinya OSAKABE

IPC: H01L23/00 ,  H03F1/56 ,  H03F3/195 ,  H03H9/05 ,  H03F3/213

CPC classification number: H01L24/14 ,  H01L21/76885 ,  H01L23/13 ,  H01L23/49822 ,  H01L23/5386 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05144 ,  H01L2224/11462 ,  H01L2224/13026 ,  H01L2224/13082 ,  H01L2224/13147 ,  H01L2224/1403 ,  H01L2224/16225 ,  H01L2924/12042 ,  H01L2924/30101 ,  H01L2924/351 ,  H03F1/56 ,  H03F3/195 ,  H03F3/213 ,  H03F2200/222 ,  H03F2200/318 ,  H03F2200/451 ,  H03H9/0514 ,  H03H9/059 ,  H01L2924/00

Abstract: A bump-equipped electronic component includes a circuit substrate and first and second bumps which are disposed on a principal surface of the circuit substrate and have different cross-sectional areas in a direction parallel or substantially parallel to the principal surface. One of the first and second bumps having a smaller cross-sectional area includes a height adjustment layer disposed in a direction perpendicular or substantially perpendicular to the principal surface.

公开(公告)号：US20140151874A1

公开(公告)日：2014-06-05

申请号：US14096044

申请日：2013-12-04

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Isao OBU ,  Shinya OSAKABE

IPC: H01L23/498 ,  H01L21/768

CPC classification number: H01L24/14 ,  H01L21/76885 ,  H01L23/13 ,  H01L23/49822 ,  H01L23/5386 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05144 ,  H01L2224/11462 ,  H01L2224/13026 ,  H01L2224/13082 ,  H01L2224/13147 ,  H01L2224/1403 ,  H01L2224/16225 ,  H01L2924/12042 ,  H01L2924/30101 ,  H01L2924/351 ,  H03F1/56 ,  H03F3/195 ,  H03F3/213 ,  H03F2200/222 ,  H03F2200/318 ,  H03F2200/451 ,  H03H9/0514 ,  H03H9/059 ,  H01L2924/00

Abstract: A bump-equipped electronic component includes a circuit substrate and first and second bumps which are disposed on a principal surface of the circuit substrate and have different cross-sectional areas in a direction parallel or substantially parallel to the principal surface. One of the first and second bumps having a smaller cross-sectional area includes a height adjustment layer disposed in a direction perpendicular or substantially perpendicular to the principal surface.

Abstract translation: 配有凸块的电子部件包括电路基板和设置在电路基板的主表面上并且在与主表面平行或基本平行的方向上具有不同横截面积的第一和第二凸块。 具有较小横截面积的第一和第二凸块中的一个包括沿与主表面垂直或基本垂直的方向设置的高度调节层。

公开(公告)号：US20210359114A1

公开(公告)日：2021-11-18

申请号：US17386462

申请日：2021-07-27

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Yasunari UMEMOTO ,  Isao OBU ,  Kaoru IDENO ,  Shigeki KOYA

IPC: H01L29/737 ,  H01L29/423 ,  H01L29/417

Abstract: A collector layer, a base layer, and an emitter layer that are disposed on a substrate form a bipolar transistor. An emitter electrode is in ohmic contact with the emitter layer. The emitter layer has a shape that is long in one direction in plan view. A difference in dimension with respect to a longitudinal direction of the emitter layer between the emitter layer and an ohmic contact interface at which the emitter layer and the emitter electrode are in ohmic contact with each other is larger than a difference in dimension with respect to a width direction of the emitter layer between the emitter layer and the ohmic contact interface.

公开(公告)号：US20210320194A1

公开(公告)日：2021-10-14

申请号：US17355048

申请日：2021-06-22

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Isao OBU ,  Yasunari UMEMOTO ,  Takayuki TSUTSUI ,  Satoshi TANAKA

IPC: H01L29/73 ,  H01L29/205 ,  H01L29/08 ,  H01L29/417 ,  H01L29/737 ,  H01L21/8252 ,  H01L21/285 ,  H01L21/306 ,  H01L21/308 ,  H01L29/66 ,  H01L27/082

Abstract: A first sub-collector layer functions as an inflow path of a collector current that flows in a collector layer of a heterojunction bipolar transistor. A collector ballast resistor layer having a lower doping concentration than the first sub-collector layer is disposed between the collector layer and the first sub-collector layer.