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    POWER AMPLIFIER MODULE
    2.
    发明申请
    POWER AMPLIFIER MODULE 有权

    公开(公告)号：US20220060158A1

    公开(公告)日：2022-02-24

    申请号：US17453962

    申请日：2021-11-08

    Applicant: Murata Manufacturing Co., Ltd.

    Inventor： Shigeki KOYA ,  Yasunari UMEMOTO ,  Yuichi SAITO ,  Isao OBU ,  Takayuki TSUTSUI

    IPC: H03F3/21 ,  H01F17/00 ,  H01L23/00 ,  H01L23/552 ,  H03F3/213 ,  H03F1/02 ,  H01L23/66 ,  H01L23/498

    Abstract: A power amplifier module includes a first substrate and a second substrate, at least part of the second substrate being disposed in a region overlapping the first substrate. The second substrate includes a first amplifier circuit and a second amplifier circuit. The first substrate includes a first transformer including a primary winding having a first end and a second end and a secondary winding having a first end and a second end; a second transformer including a primary winding having a first end and a second end and a secondary winding having a first end and a second end; and multiple first conductors disposed in a row between the first transformer and the second transformer, each of the multiple first conductors extending from the wiring layer on a first main surface to the wiring layer on a second main surface of the substrate.

    SEMICONDUCTOR DEVICE
    3.
    发明申请
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20200006265A1

    公开(公告)日：2020-01-02

    申请号：US16452637

    申请日：2019-06-26

    Applicant: Murata Manufacturing Co., Ltd.

    Inventor： Kazuya KOBAYASHI ,  Atsushi KUROKAWA ,  Hiroaki TOKUYA ,  Isao OBU ,  Yuichi SAITO

    IPC: H01L23/00 ,  H01L49/02 ,  H01L23/31 ,  H01L27/06 ,  H01L23/528

    Abstract: A target element to be protected and a protrusion are arranged on a substrate. An insulating film arranged on the substrate covers the target element and at least a side surface of the protrusion. An electrode pad for external connection is arranged on the insulating film. The electrode pad at least partially overlaps the target element and the protrusion as seen in plan view. A maximum distance between the upper surface of the protrusion and the electrode pad in the height direction is shorter than a maximum distance between the upper surface of the target element and the electrode pad in the height direction.

    HETEROJUNCTION BIPOLAR TRANSISTOR
    6.
    发明申请
    HETEROJUNCTION BIPOLAR TRANSISTOR 有权
    异相双极晶体管

    公开(公告)号：US20160005841A1

    公开(公告)日：2016-01-07

    申请号：US14848090

    申请日：2015-09-08

    Applicant: MURATA MANUFACTURING CO., LTD.

    Inventor： Isao OBU ,  Yasunari UMEMOTO ,  Atsushi KUROKAWA

    IPC: H01L29/737 ,  H01L29/10 ,  H01L29/205 ,  H01L29/08

    CPC classification number: H01L29/7378 ,  H01L29/0817 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/205 ,  H01L29/41758 ,  H01L29/66318 ,  H01L29/7371

    Abstract: A heterojunction bipolar transistor includes a collector layer composed of a semiconductor containing GaAs as a main component; a base layer including a first base layer and a second base layer the first base layer forming a heterojunction with the collector layer and being composed of a semiconductor containing a material as a main component, the material being lattice-mismatched to the main component of the collector layer, the first base layer having a film thickness less than a critical thickness at which a misfit dislocation is introduced, the second base layer being joined to the first base layer and composed of a semiconductor containing a material as a main component, and the material being lattice-matched to the main component of the collector layer; and an emitter layer that forms a heterojunction with the second base layer.

    Abstract translation: 异质结双极晶体管包括由包含GaAs作为主要成分的半导体构成的集电极层; 基底层，包括第一基底层和第二基底层，所述第一基底层与所述集电体层形成异质结，并且由包含材料作为主要成分的半导体构成，所述材料与所述第一基底层的主要成分晶格错配 所述第一基底层的膜厚小于引入失配位错的临界厚度，所述第二基底层被接合到所述第一基底层并且由包含材料作为主要成分的半导体构成， 材料与集电极层的主要成分晶格匹配; 以及与第二基极层形成异质结的发射极层。

    SEMICONDUCTOR DEVICE
    7.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20220231150A1

    公开(公告)日：2022-07-21

    申请号：US17714860

    申请日：2022-04-06

    Applicant: Murata Manufacturing Co., Ltd.

    Inventor： Yasunari UMEMOTO ,  Isao OBU ,  Kaoru IDENO ,  Shigeki KOYA

    IPC: H01L29/737 ,  H01L29/423 ,  H01L29/417

    Abstract: A collector layer, a base layer, and an emitter layer that are disposed on a substrate form a bipolar transistor. An emitter electrode is in ohmic contact with the emitter layer. The emitter layer has a shape that is long in one direction in plan view. A difference in dimension with respect to a longitudinal direction of the emitter layer between the emitter layer and an ohmic contact interface at which the emitter layer and the emitter electrode are in ohmic contact with each other is larger than a difference in dimension with respect to a width direction of the emitter layer between the emitter layer and the ohmic contact interface.

    SEMICONDUCTOR DEVICE
    8.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20220115272A1

    公开(公告)日：2022-04-14

    申请号：US17559958

    申请日：2021-12-22

    Applicant: Murata Manufacturing Co., Ltd.

    Inventor： Yasunari UMEMOTO ,  Shigeki KOYA ,  Isao OBU ,  Kaoru IDENO

    IPC: H01L21/8252 ,  H01L29/66 ,  H01L29/737 ,  H01L29/15

    Abstract: A collector layer, a base layer, an emitter layer, and an emitter mesa layer are placed above a substrate in this order. A base electrode and an emitter electrode are further placed above the substrate. The emitter mesa layer has a long shape in a first direction in plan view. The base electrode includes a base electrode pad portion spaced from the emitter mesa layer in the first direction. An emitter wiring line and a base wiring line are placed on the emitter electrode and the base electrode, respectively. The emitter wiring line is connected to the emitter electrode via an emitter contact hole. In the first direction, the spacing between the edges of the emitter mesa layer and the emitter contact hole on the side of the base wiring line is smaller than that between the emitter mesa layer and the base wiring line.

    SEMICONDUCTOR DEVICE AND AMPLIFIER MODULE
    9.
    发明申请
    SEMICONDUCTOR DEVICE AND AMPLIFIER MODULE 审中-公开

    公开(公告)号：US20200303372A1

    公开(公告)日：2020-09-24

    申请号：US16820441

    申请日：2020-03-16

    Applicant: Murata Manufacturing Co., Ltd.

    Inventor： Kenji SASAKI ,  Masao KONDO ,  Shigeki KOYA ,  Shinnosuke TAKAHASHI ,  Yasunari UMEMOTO ,  Isao OBU ,  Takayuki TSUTSUI

    IPC: H01L27/082 ,  H03F3/195 ,  H03F3/213 ,  H01L29/737

    Abstract: A semiconductor device includes two cell rows, each of which is formed of a plurality of transistor cells aligned in parallel to each other. Each of the plurality of transistor cells includes a collector region, a base region, and an emitter region that are disposed above a substrate. A plurality of collector extended wiring lines are each connected to the collector region of a corresponding one of the plurality of transistor cells and are extended in a direction intersecting an alignment direction of the plurality of transistor cells. A collector integrated wiring line connects the plurality of collector extended wiring lines to each other. A collector intermediate integrated wiring line that is disposed between the two cell rows in plan view connects the plurality of collector extended wring lines extended from the plurality of transistor cells that belong to one of the two cell rows to each other.

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