公开(公告)号：US20240204087A1

公开(公告)日：2024-06-20

申请号：US18593387

申请日：2024-03-01

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Yasunari UMEMOTO ,  Isao OBU ,  Kaoru IDENO ,  Shigeki KOYA

IPC: H01L29/737 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/423

CPC classification number: H01L29/7371 ,  H01L29/41708 ,  H01L29/42304 ,  H01L29/0692 ,  H01L29/0817

Abstract: A collector layer, a base layer, and an emitter layer that are disposed on a substrate form a bipolar transistor. An emitter electrode is in ohmic contact with the emitter layer. The emitter layer has a shape that is long in one direction in plan view. A difference in dimension with respect to a longitudinal direction of the emitter layer between the emitter layer and an ohmic contact interface at which the emitter layer and the emitter electrode are in ohmic contact with each other is larger than a difference in dimension with respect to a width direction of the emitter layer between the emitter layer and the ohmic contact interface.

公开(公告)号：US20230318543A1

公开(公告)日：2023-10-05

申请号：US18328653

申请日：2023-06-02

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Shigeki KOYA ,  Shaojun MA ,  Shinnosuke TAKAHASHI

IPC: H03F3/21 ,  H01L29/732

CPC classification number: H03F3/21 ,  H01L29/7325 ,  H03F2200/451

Abstract: A power amplifier comprising amplifier circuits of multiple stages. Each of the amplifier circuits of multiple stages includes a bipolar transistor and a base electrode. The bipolar transistor included in each of the amplifier circuits of multiple stages includes a collector layer, a base layer placed on the collector layer, and an emitter mesa placed on part of the region of the base layer. The emitter mesa has a shape elongated in one direction in plan view. The base electrode includes a base main portion arranged in such a manner as to be separated from the emitter mesa with a gap in a direction orthogonal to a lengthwise direction of the emitter mesa in plan view. The base main portion has a shape elongated in a direction parallel to the lengthwise direction of the emitter mesa in plan view and is electrically connected to the base layer.

公开(公告)号：US20220060158A1

公开(公告)日：2022-02-24

申请号：US17453962

申请日：2021-11-08

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Shigeki KOYA ,  Yasunari UMEMOTO ,  Yuichi SAITO ,  Isao OBU ,  Takayuki TSUTSUI

IPC: H03F3/21 ,  H01F17/00 ,  H01L23/00 ,  H01L23/552 ,  H03F3/213 ,  H03F1/02 ,  H01L23/66 ,  H01L23/498

Abstract: A power amplifier module includes a first substrate and a second substrate, at least part of the second substrate being disposed in a region overlapping the first substrate. The second substrate includes a first amplifier circuit and a second amplifier circuit. The first substrate includes a first transformer including a primary winding having a first end and a second end and a secondary winding having a first end and a second end; a second transformer including a primary winding having a first end and a second end and a secondary winding having a first end and a second end; and multiple first conductors disposed in a row between the first transformer and the second transformer, each of the multiple first conductors extending from the wiring layer on a first main surface to the wiring layer on a second main surface of the substrate.

公开(公告)号：US20220059427A1

公开(公告)日：2022-02-24

申请号：US17370953

申请日：2021-07-08

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Masao KONDO ,  Kenji SASAKI ,  Shigeki KOYA

IPC: H01L23/367 ,  H01L23/498 ,  H01L23/00 ,  H01L23/42 ,  H01L23/31 ,  H01L23/055 ,  H01L25/18 ,  H05K1/18 ,  H05K1/11

Abstract: A semiconductor package includes a module substrate having opposite top and bottom surfaces, a semiconductor chip provided with bumps and mounted on the top surface of the module substrate via the bumps, and a metal member having a top portion disposed at a level higher than the semiconductor chip with reference to the top surface of the module substrate and including the semiconductor chip in plan view and a side portion extending from the top portion toward the module substrate. The module substrate includes a first metal film disposed on or in at least one of the bottom surface and an internal layer of the module substrate. The first metal film is electrically connected to the bumps and reaches a side surface of the module substrate. The side portion is thermally coupled to the first metal film at the side surface of the module substrate.

公开(公告)号：US20210134788A1

公开(公告)日：2021-05-06

申请号：US17149851

申请日：2021-01-15

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Shigeki KOYA ,  Takayuki TSUTSUI ,  Kazuhito NAKAI ,  Yusuke TANAKA

IPC: H01L27/06 ,  H01L23/522 ,  H01L23/528 ,  H01L29/66

Abstract: A semiconductor device includes a plurality of unit transistors that are arranged on a surface of a substrate in a first direction. Input capacitive elements are arranged so as to correspond to the unit transistors. An emitter common wiring line is connected to emitter layers of the unit transistors. A via-hole extending from the emitter common wiring line to a back surface of the substrate is disposed at a position overlapping the emitter common wiring line. A collector common wiring line is connected to collector layers of the unit transistors. The input capacitive elements, the emitter common wiring line, the unit transistors, and the collector common wiring line are arranged in this order in a second direction. Base wiring lines that connect the input capacitive elements to base layers of the corresponding unit transistors intersect the emitter common wiring line without physical contact.

公开(公告)号：US20210098403A1

公开(公告)日：2021-04-01

申请号：US16994187

申请日：2020-08-14

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Masao KONDO ,  Kenji SASAKI ,  Shigeki KOYA ,  Shinnosuke TAKAHASHI

IPC: H01L23/00

Abstract: Two transistor rows are arranged on or in a substrate. Each of the two transistor rows is configured by a plurality of transistors aligned in a first direction, and the two transistor rows are arranged at an interval in a second direction orthogonal to the first direction. A first wiring is arranged between the two transistor rows when seen from above. The first wiring is connected to collectors or drains of the plurality of transistors in the two transistor rows. The first bump overlaps with the first wiring when seen from above, is arranged between the two transistor rows, and is connected to the first wiring.

公开(公告)号：US20210083080A1

公开(公告)日：2021-03-18

申请号：US17002618

申请日：2020-08-25

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Kenji SASAKI ,  Yasunari UMEMOTO ,  Shigeki KOYA ,  Shinnosuke TAKAHASHI ,  Masao KONDO

IPC: H01L29/737 ,  H01L29/06 ,  H01L29/08 ,  H01L29/205 ,  H01L29/417 ,  H01L27/02 ,  H01L23/00 ,  H01L23/528 ,  H03K17/60

Abstract: An electrically conductive sub-collector layer is provided in a surface layer portion of a substrate. A collector layer, a base layer, and an emitter layer are located within the sub-collector layer when viewed in plan. The collector layer is connected to the sub-collector layer. An emitter electrode and a base electrode are long in a first direction when viewed in plan. The emitter electrode overlaps the emitter layer. The base electrode and the emitter electrode are discretely located away from each other in a second direction orthogonal to the first direction. A collector electrode is located on one side in the second direction with respect to the emitter electrode and is not located on the other side when viewed in plan. A base line is connected to the base electrode in a manner so as to adjoin a portion other than longitudinal ends of the base electrode.

公开(公告)号：US20200006536A1

公开(公告)日：2020-01-02

申请号：US16568154

申请日：2019-09-11

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Kenji SASAKI ,  Kingo KUROTANI ,  Takashi KITAHARA ,  Shigeki KOYA

IPC: H01L29/737 ,  H03F3/19 ,  H01L23/00 ,  H01L23/482 ,  H01L29/417 ,  H01L29/06 ,  H01L23/535 ,  H01L27/082 ,  H01L29/40

Abstract: A semiconductor device includes a heterojunction bipolar transistor and a bump. The heterojunction bipolar transistor (HBT) includes a plurality of unit transistors. The bump is electrically connected to emitters of the plurality of unit transistors through respective overlying conductor filled via openings that overlap in a plan view with a width portion of the bump. The semiconductor device reduces heat resistance in an HBT cell by satisfying two conditions, the first of which is related to specific sizing and positioning of a width portion of the overlying via opening relative to the width portion of the bump, and the second of which is related to positioning the base electrode entirely within a specific region of the width portion of the overlapping overlying via opening.

公开(公告)号：US20210327775A1

公开(公告)日：2021-10-21

申请号：US17224784

申请日：2021-04-07

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Shigeki KOYA ,  Yoshimitsu TAKENOUCHI ,  Kenji SASAKI ,  Masao KONDO

IPC: H01L23/13 ,  H05K1/02 ,  H01L23/00

Abstract: An amplifier IC mounted on a multilayer board includes input, output, and common terminals. The multilayer board includes common, input, and output terminals on board side. These terminals are connected to the corresponding terminals on device side via bumps. On the lower surface of the multilayer board, a lower surface common terminal is arranged at a location overlapping the common terminal in plan view. First, second, and third via conductors are sequentially arranged toward the lower surface common terminal from the common terminal. An input via conductor is connected to the input terminal on board side. In plan view, the area of the first common via conductor is larger than any one of the areas of the second and third common via conductors and the input via conductor. In plan view, the area of bump of the common terminal is larger than the area of bump of the input terminal.

公开(公告)号：US20210234026A1

公开(公告)日：2021-07-29

申请号：US17229564

申请日：2021-04-13

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Yasunari UMEMOTO ,  Shigeki KOYA ,  Atsushi KUROKAWA

IPC: H01L29/737 ,  H01L29/06 ,  H01L29/08 ,  H01L29/36 ,  H01L29/66 ,  H01L29/10

Abstract: A bipolar transistor comprising a subcollector layer, and a collector layer on the subcollector layer. The collector layer includes a plurality of doped layers. The plurality of doped layers includes a first doped layer that has a highest impurity concentration thereamong and is on a side of or in contact with the subcollector layer. Also, the first doped layer includes a portion that extends beyond at least one edge of the plurality of doped layers in a cross-sectional view.