公开(公告)号：US20220077109A1

公开(公告)日：2022-03-10

申请号：US17015308

申请日：2020-09-09

Applicant: QUALCOMM Incorporated

Inventor： Bharani CHAVA ,  Stanley Seungchul SONG ,  Abinash ROY ,  Jonghae KIM

IPC: H01L25/065 ,  H01L23/00 ,  H01L21/78 ,  H01L25/00

Abstract: An integrated circuit (IC) package is described. The IC package includes a first die having a first power delivery network on the first die. The IC package also includes a second die having a second power delivery network on the second die. The first die is stacked on the second die. The IC package further includes package voltage regulators integrated with and coupled to the first die and/or the second die within a package core of the integrated circuit package.

公开(公告)号：US20220013444A1

公开(公告)日：2022-01-13

申请号：US16927823

申请日：2020-07-13

Applicant: QUALCOMM Incorporated

Inventor： Jonghae KIM ,  Milind SHAH ,  Periannan CHIDAMBARAM

IPC: H01L23/498 ,  H03F3/213

Abstract: A package that includes a power amplifier and a substrate coupled to the power amplifier. The substrate includes an encapsulation layer, a capacitor device located in the encapsulation layer, an inductor located in the encapsulation layer, at least one first dielectric layer coupled to a first surface of the encapsulation layer, and a plurality of first interconnects coupled to the first surface of the encapsulation layer. The plurality of first interconnects is located at least in the at least one first dielectric layer. The plurality of first interconnects is coupled to the capacitor device and the inductor. The inductor and the capacitor device are configured to be electrically coupled together to operate as elements of a matching network for the power amplifier. The capacitor device is configured to be coupled to ground.

公开(公告)号：US20210391234A1

公开(公告)日：2021-12-16

申请号：US16898096

申请日：2020-06-10

Applicant: QUALCOMM Incorporated

Inventor： Je-Hsiung LAN ,  Jonghae KIM ,  Ranadeep DUTTA

IPC: H01L23/367 ,  H01L23/373 ,  H01L21/48

Abstract: A semiconductor package is described. The semiconductor package includes a passive substrate and a first integrated passive device (IPD) in a first interlayer-dielectric (ILD) layer on the passive substrate. The semiconductor package also includes a second ILD layer on the first ILD layer. The semiconductor package further includes a second IPD in a third ILD layer on the second ILD layer. The semiconductor package also includes a thermal mitigation structure on inductive elements of the second IPD.

公开(公告)号：US20210281234A1

公开(公告)日：2021-09-09

申请号：US16812294

申请日：2020-03-07

Applicant: QUALCOMM Incorporated

Inventor： Jonghae KIM ,  Milind SHAH ,  Periannan CHIDAMBARAM

IPC: H03H7/01 ,  H01L49/02 ,  H01F17/00 ,  H01L27/06

Abstract: An improved filter for high frequency, such as 5G wireless communication, may include inductor-Q improvement and reduced die-size with a hybrid 3D-inductor integration. In some examples, the inductors may be formed using an IPD and a fan-out package. For instance, a first multilayer substrate comprises a plurality of metal insulator metal (MIM) capacitors formed using various layers (e.g., M1 and M2) and a first portion of the 3D inductors, and a second multilayer substrate comprises at least a second portion of the 3D inductors. The 3D inductors may be electrically coupled to the MIM capacitors to form at least one filter network.

公开(公告)号：US20210234526A1

公开(公告)日：2021-07-29

申请号：US16750625

申请日：2020-01-23

Applicant: QUALCOMM Incorporated

Inventor： Jonghae KIM ,  Milind SHAH ,  Periannan CHIDAMBARAM

IPC: H03H7/38 ,  H01Q1/22 ,  H01Q1/52 ,  H04B1/40

Abstract: Impedance matching transceivers may include a tuning circuit to match the transceiver module impedance to the housing conditions. In some examples, the impedance matching is controlled by tuning-circuits that may be integrated into a transceiver module by using a fan-out package (FO PKG). One example of a tuning circuit may include a switch to isolate the parallel capacitors, such that when the switch is on or closed the parallel capacitors are active.

公开(公告)号：US20200381398A1

公开(公告)日：2020-12-03

申请号：US16600300

申请日：2019-10-11

Applicant: QUALCOMM Incorporated

Inventor： Je-Hsiung LAN ,  Jonghae KIM ,  Ranadeep DUTTA

IPC: H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L23/48 ,  H01L25/00

Abstract: 3D integrated circuit (3DIC) device architecture is disclosed for monolithically heterogeneous integration of III-V devices over Si-CMOS devices with high-quality (HQ) integrated passives devices (IPD) or re-distributed layers (RDL). In addition, a thermal spreader may be added over the upper III-V tier to enhance device power performance (e.g., PAE for PA) and device reliability (e.g., with a reduced Tj/junction temperature).

公开(公告)号：US20200350425A1

公开(公告)日：2020-11-05

申请号：US16401240

申请日：2019-05-02

Applicant: QUALCOMM Incorporated

Inventor： Ranadeep DUTTA ,  Jonghae KIM ,  Je-Hsiung LAN

IPC: H01L29/778 ,  H01L29/66 ,  H01L27/088 ,  H01L29/16 ,  H01L29/20

Abstract: A semiconductor device having heterogeneous transistors integrated on a diamond substrate. An example semiconductor device generally includes a diamond substrate, a first transistor disposed above the diamond substrate, the first transistor comprising gallium nitride, and a second transistor disposed above the diamond substrate, the second transistor comprising a different semiconductor than the first transistor.

公开(公告)号：US20200020473A1

公开(公告)日：2020-01-16

申请号：US16035378

申请日：2018-07-13

Applicant: QUALCOMM Incorporated

Inventor： Changhan Hobie YUN ,  Mario Francisco VELEZ ,  Nosun PARK ,  Wei-Chuan CHEN ,  Niranjan Sunil MUDAKATTE ,  Xiaoju YU ,  Paragkumar Ajaybhai THADESAR ,  Jonghae KIM

IPC: H01F17/00 ,  H01L49/02 ,  H01L23/522 ,  H01L27/02

Abstract: Aspects of the present disclosure provide three-dimensional (3D) through-glass-via (TGV) inductors for use in electronic devices. In some embodiments, a first portion of a 3D TGV inductor may be formed in a first wafer and a second portion of a 3D TGV may be formed in a second wafer. The first portion and second portion may be bonded together in a bonded wafer device thereby forming a larger inductor occupying relatively little wafer space on the first and the second wafers.

公开(公告)号：US20190259780A1

公开(公告)日：2019-08-22

申请号：US16402713

申请日：2019-05-03

Applicant: QUALCOMM Incorporated

Inventor： Shiqun GU ,  Daniel Daeik KIM ,  Matthew Michael NOWAK ,  Jonghae KIM ,  Changhan Hobie YUN ,  Je-Hsiung Jeffrey LAN ,  David Francis BERDY

IPC: H01L27/12 ,  H01L23/498 ,  H01L21/306 ,  H01L23/66 ,  H01L27/088 ,  H01L21/304 ,  H01L21/8234 ,  H01L21/84 ,  H01L29/10 ,  H01L27/092 ,  H01L21/762 ,  H01L21/768 ,  H01L23/528

Abstract: An integrated circuit (IC) includes a glass substrate and a buried oxide layer. The IC additionally includes a first semiconductor device coupled to the glass substrate. The first semiconductor device includes a first gate and a first portion of a semiconductive layer coupled to the buried oxide layer. The first gate is located between the glass substrate and the first portion of the semiconductive layer and between the glass substrate and the buried oxide layer. The IC additionally includes a second semiconductor device coupled to the glass substrate. The second semiconductor device includes a second gate and a second portion of the semiconductive layer. The second gate is located between the glass substrate and the second portion of the semiconductive layer. The first portion is discontinuous from the second portion.

公开(公告)号：US20180047660A1

公开(公告)日：2018-02-15

申请号：US15233906

申请日：2016-08-10

Applicant: QUALCOMM Incorporated

Inventor： Chengjie ZUO ,  Mario Francisco VELEZ ,  Changhan Hobie YUN ,  David Francis BERDY ,  Daeik Daniel KIM ,  Jonghae KIM

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/15 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L23/49805 ,  H01L21/4846 ,  H01L21/56 ,  H01L23/145 ,  H01L23/15 ,  H01L23/3121 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/645 ,  H01L24/02 ,  H05K1/0218 ,  H05K3/3436 ,  H05K2201/10719

Abstract: A device includes a passive-on-glass (POG) structure and an interface layer. The POG structure includes a passive component and at least one contact pad on a first surface of a glass substrate. The interface layer has a second surface on the first surface of the glass substrate such that the passive component and the at least one contact pad are located between the first surface of the glass substrate and the interface layer. The interface layer includes at least one land grid array (LGA) pad formed on a third surface of the interface layer, where the third surface of the interface layer is opposite the second surface of the interface layer. The interface layer also includes at least one via formed in the interface layer configured to electrically connect the at least one contact pad with the at least one LGA pad.