公开(公告)号：US20230230910A1

公开(公告)日：2023-07-20

申请号：US17579038

申请日：2022-01-19

Applicant: QUALCOMM Incorporated

Inventor： Changhan Hobie YUN ,  Nosun PARK ,  Daniel Daeik KIM ,  Paragkumar Ajaybhai THADESAR ,  Sameer Sunil VADHAVKAR

IPC: H01L23/498 ,  H01L23/48 ,  H01L23/522 ,  H01L21/48 ,  H01L23/00

CPC classification number: H01L23/49827 ,  H01L21/486 ,  H01L23/481 ,  H01L23/5223 ,  H01L23/49816 ,  H01L24/14 ,  H01L2924/15311

Abstract: A device includes a redistribution layer (RDL) substrate. The device also includes a passive component in the RDL substrate proximate a first surface of the RDL substrate. The device further includes a first die coupled to a second surface of the RDL substrate, opposite the first surface of the RDL substrate.

公开(公告)号：US20220223516A1

公开(公告)日：2022-07-14

申请号：US17149006

申请日：2021-01-14

Applicant: QUALCOMM Incorporated

Inventor： Nosun PARK ,  Changhan Hobie YUN ,  Daniel Daeik KIM ,  Sameer Sunil VADHAVKAR ,  Paragkumar Ajaybhai THADESAR

IPC: H01L23/522 ,  H01L27/01 ,  H01L21/70

Abstract: A device includes a main capacitor composed of a first plate of a first back-end-of-line (BEOL) metallization layer, a main insulator layer on the first plate, and a second plate on the main insulator layer. The second plate is composed of a second BEOL metallization layer. The device includes a first tuning capacitor of a first portion of a first BEOL interconnect trace coupled to the first plate of the main capacitor through first BEOL sideline traces. The first tuning capacitor is composed of a first insulator layer on a surface and sidewalls of the first portion of the first BEOL interconnect trace. The first tuning capacitor includes a second BEOL interconnect trace on a surface and sidewalls of the first insulator layer. The device includes a first via capture pad coupled to the second BEOL interconnect trace of the first tuning capacitor.

公开(公告)号：US20210351750A1

公开(公告)日：2021-11-11

申请号：US16870383

申请日：2020-05-08

Applicant: QUALCOMM Incorporated

Inventor： Daniel Daeik KIM ,  Paragkumar Ajaybhai THADESAR ,  Changhan Hobie YUN ,  Sameer Sunil VADHAVKAR ,  Nosun PARK

IPC: H03F3/213 ,  H03F3/195 ,  H03F1/56 ,  H01L23/66 ,  H01L23/34

Abstract: A device that includes a substrate and a power amplifier coupled to the substrate. The substrate includes at least one dielectric layer, a plurality of interconnects, and a capacitor configured to operate as an output match element, where the capacitor is defined by a plurality of capacitor interconnects. The power amplifier is coupled to the capacitor. The capacitor is configured to operate as an output match element for the power amplifier. The substrate includes an inductor coupled to the capacitor, where the inductor is defined by at least one inductor interconnect. The capacitor and the inductor are configured to operate as a resonant trap or an output match element.

公开(公告)号：US20190259780A1

公开(公告)日：2019-08-22

申请号：US16402713

申请日：2019-05-03

Applicant: QUALCOMM Incorporated

Inventor： Shiqun GU ,  Daniel Daeik KIM ,  Matthew Michael NOWAK ,  Jonghae KIM ,  Changhan Hobie YUN ,  Je-Hsiung Jeffrey LAN ,  David Francis BERDY

IPC: H01L27/12 ,  H01L23/498 ,  H01L21/306 ,  H01L23/66 ,  H01L27/088 ,  H01L21/304 ,  H01L21/8234 ,  H01L21/84 ,  H01L29/10 ,  H01L27/092 ,  H01L21/762 ,  H01L21/768 ,  H01L23/528

Abstract: An integrated circuit (IC) includes a glass substrate and a buried oxide layer. The IC additionally includes a first semiconductor device coupled to the glass substrate. The first semiconductor device includes a first gate and a first portion of a semiconductive layer coupled to the buried oxide layer. The first gate is located between the glass substrate and the first portion of the semiconductive layer and between the glass substrate and the buried oxide layer. The IC additionally includes a second semiconductor device coupled to the glass substrate. The second semiconductor device includes a second gate and a second portion of the semiconductive layer. The second gate is located between the glass substrate and the second portion of the semiconductive layer. The first portion is discontinuous from the second portion.

公开(公告)号：US20220069193A1

公开(公告)日：2022-03-03

申请号：US17005168

申请日：2020-08-27

Applicant: QUALCOMM Incorporated

Inventor： Changhan Hobie YUN ,  Nosun PARK ,  Daniel Daeik KIM ,  Paragkumar Ajaybhai THADESAR ,  Sameer Sunil VADHAVKAR

IPC: H01L41/08 ,  H03H9/02

Abstract: A package that includes an integrated device, an integrated passive device and a void. The integrated device is configured as a filter. The integrated device includes a substrate comprising a piezoelectric material, and at least one metal layer coupled to a first surface of the first substrate. The integrated passive device is coupled to the integrated device. The integrated passive device is configured as a cap for the integrated device. The void is located between the integrated device and the integrated passive device.

公开(公告)号：US20210249177A1

公开(公告)日：2021-08-12

申请号：US16788484

申请日：2020-02-12

Applicant: QUALCOMM Incorporated

Inventor： Chunhu ZHANG ,  Ravi Kiran CHALLA ,  Daniel Daeik KIM ,  Chandra Sekhar Reddy KAIPA

IPC: H01F27/28 ,  H01Q7/04 ,  H01F41/04

Abstract: Certain aspects of the present disclosure generally relate to an electronic device having an inductive element made up of a plurality of metal layers including a metal shielding layer with one or more electrically floating metal pieces. One example electronic device has a plurality of metal layers that generally includes a bottom metal layer, one or more middle metal layers disposed above the bottom metal layer, wherein at least one of the middle layers comprises a coil, and a top metal layer disposed above the one or more middle metal layers. At least one of the bottom metal layer or the top metal layer comprises a shield layer. At least a first portion of a first region of the shield layer overlying or underlying the coil comprises one or more metal pieces that are electrically floating and are disconnected from the shield layer.

公开(公告)号：US20190252316A1

公开(公告)日：2019-08-15

申请号：US16254735

申请日：2019-01-23

Applicant: QUALCOMM Incorporated

Inventor： Shu ZHANG ,  Daniel Daeik KIM ,  Chenqian GAN ,  Bonhoon KOO ,  Babak NEJATI

IPC: H01L23/522 ,  H01L49/02 ,  H01L23/64 ,  H01F27/28 ,  H01F41/04

CPC classification number: H01L23/5227 ,  H01F17/0013 ,  H01F17/02 ,  H01F27/2804 ,  H01F41/042 ,  H01F2017/002 ,  H01F2017/0073 ,  H01F2027/2809 ,  H01L23/52 ,  H01L23/645 ,  H01L28/10

Abstract: Some features pertain to a substrate, and a first inductor integrated into the substrate. The first inductor includes a plurality of first inductor windings in a first metal layer and a second metal layer. A second inductor is integrated into the substrate. The second inductor includes a first spiral in a third metal layer. The first spiral is located at least partially inside the plurality of first inductor windings, wherein the second inductor is perpendicular to the first inductor.

公开(公告)号：US20230352423A1

公开(公告)日：2023-11-02

申请号：US17661029

申请日：2022-04-27

Applicant: QUALCOMM Incorporated

Inventor： Sameer Sunil VADHAVKAR ,  Changhan Hobie YUN ,  Paragkumar Ajaybhai THADESAR ,  Nosun PARK ,  Daniel Daeik KIM

IPC: H01L23/00 ,  H01L21/78 ,  H01L21/304

CPC classification number: H01L23/562 ,  H01L21/78 ,  H01L21/304

Abstract: Disclosed is a device that includes a die and a protection layer surrounding the die. The protection layer is applied at a backend process prior to dicing a wafer to individual dies. The protection layer protects the die from chips and cracks during and after dicing the wafer.

公开(公告)号：US20230187340A1

公开(公告)日：2023-06-15

申请号：US17547093

申请日：2021-12-09

Applicant: QUALCOMM Incorporated

Inventor： Nosun PARK ,  Changhan Hobie YUN ,  Daniel Daeik KIM ,  Paragkumar Ajaybhai THADESAR ,  Sameer Sunil VADHAVKAR

IPC: H01L23/522 ,  H01L49/02

CPC classification number: H01L23/5223 ,  H01L23/5227 ,  H01L28/40 ,  H01L28/10

Abstract: An integrated circuit (IC) includes a substrate and a first metal-insulator-metal (MIM) capacitor. The first MIM capacitor includes a first plate comprising a first metallization layer on a surface of the substrate. The first MIM capacitor also includes a first MIM insulator layer on a first portion of a surface of the first plate, a sidewall of the first plate, and a first portion of the surface of the substrate. The first MIM capacitor further includes a second plate on the first MIM insulator layer and on a second portion of the surface of the substrate, the second plate comprising a second metallization layer. The IC also includes an inductor comprising a portion of the second plate on the second portion of the surface of the substrate.

公开(公告)号：US20220069453A1

公开(公告)日：2022-03-03

申请号：US17002594

申请日：2020-08-25

Applicant: QUALCOMM Incorporated

Inventor： Changhan Hobie YUN ,  Daniel Daeik KIM ,  Paragkumar Ajaybhai THADESAR ,  Nosun PARK ,  Sameer Sunil VADHAVKAR

IPC: H01Q1/38 ,  H04B3/52 ,  H04B3/56 ,  H01Q13/02 ,  H01Q21/28

Abstract: A substrate that includes at least one dielectric layer, a plurality of interconnects, and a curved antenna coupled to a surface of the substrate. The curved antenna is curved relative to the surface of the substrate such that at least part of the curved antenna is offset from the surface of the substrate. The substrate includes a first antenna dielectric layer coupled to the surface of the substrate, an antenna ground interconnect coupled to the first antenna dielectric layer, and a second antenna dielectric layer coupled to the antenna ground interconnect. The antenna ground interconnect configured to be coupled to ground. The curved antenna is coupled to the second antenna dielectric layer.