公开(公告)号：US20190208645A1

公开(公告)日：2019-07-04

申请号：US16298896

申请日：2019-03-11

Applicant: Sanmina Corporation

Inventor： Shinichi Iketani ,  Dale Kersten

IPC: H05K3/42 ,  H05K1/11

CPC classification number: H05K3/429 ,  H05K1/116 ,  H05K3/0094 ,  Y10T29/49165

Abstract: Laminate structures including hole plugs, and methods for forming a hole plug in a laminate structure are provided. A laminate structure may be formed with at least a dielectric layer and a first conductive foil on a first side of the dielectric layer. A blind hole may be formed in the laminate structure extending toward the first conductive foil from a second side of the dielectric layer and at least partially through the dielectric layer, the blind hole including a hole depth to hole diameter aspect ratio of less than ten (10) to one (1). Via fill ink may be disposed in the blind hole, and the via fill ink may be dried and/or cured to form a hole plug.

公开(公告)号：US10201085B2

公开(公告)日：2019-02-05

申请号：US15928042

申请日：2018-03-21

Applicant: SANMINA CORPORATION

Inventor： Shinichi Iketani

IPC: H05K1/11 ,  H05K3/02 ,  H05K3/42 ,  H05K3/00 ,  H05K3/46 ,  H05K3/06

Abstract: A multilayer PCB having may include a first sub-composite core having a first core structure sandwiched between a first conductive layer and a second conductive layer, the first core structure including one or more dielectric and conductive layers. A first via hole extends at least partially through the first core structure, wherein an inner surface of the first via hole is plated with a conductive material along a first via segment electrically coupling the first conductive layer to an internal layer or trace within the first core structure. A second via segment extending between the second conductive layer and the internal layer or trace is devoid of the conductive material such that the first via hole is substantially stub free. A first dielectric layer is coupled to the second conductive layer. A second sub-composite core coupled to the first dielectric layer.

公开(公告)号：US10123432B2

公开(公告)日：2018-11-06

申请号：US15723135

申请日：2017-10-02

Applicant: SANMINA CORPORATION

Inventor： Shinichi Iketani ,  Dale Kersten

IPC: H05K3/42 ,  H05K1/11 ,  H05K1/02

Abstract: A multilayer printed circuit board is provided having a first dielectric layer and a first plating resist selectively positioned in the first dielectric layer. A second plating resist may be selectively positioned in the first dielectric layer or a second dielectric layer, the second plating resist separate from the first plating resist. A through hole extends through the first dielectric layer, the first plating resist, and the second plating resist. An interior surface of the through hole is plated with a conductive material except along a length between the first plating resist and the second plating resist. This forms a partitioned plated through hole having a first via segment electrically isolated from a second via segment.

公开(公告)号：US20180279473A1

公开(公告)日：2018-09-27

申请号：US15928042

申请日：2018-03-21

Applicant: SANMINA CORPORATION

Inventor： Shinichi Iketani

IPC: H05K1/11 ,  H05K3/42 ,  H05K3/00 ,  H05K3/46 ,  H05K3/06

CPC classification number: H05K1/115 ,  H05K3/0047 ,  H05K3/02 ,  H05K3/06 ,  H05K3/4069 ,  H05K3/423 ,  H05K3/428 ,  H05K3/429 ,  H05K3/4623 ,  H05K3/4652 ,  H05K2201/09509 ,  H05K2203/0207 ,  H05K2203/061 ,  H05K2203/0723

Abstract: A multilayer PCB having may include a first sub-composite core having a first core structure sandwiched between a first conductive layer and a second conductive layer, the first core structure including one or more dielectric and conductive layers. A first via hole extends at least partially through the first core structure, wherein an inner surface of the first via hole is plated with a conductive material along a first via segment electrically coupling the first conductive layer to an internal layer or trace within the first core structure. A second via segment extending between the second conductive layer and the internal layer or trace is devoid of the conductive material such that the first via hole is substantially stub free. A first dielectric layer is coupled to the second conductive layer. A second sub-composite core coupled to the first dielectric layer.

公开(公告)号：US20180110133A1

公开(公告)日：2018-04-19

申请号：US15784070

申请日：2017-10-13

Applicant: SANMINA CORPORATION

Inventor： Shinichi Iketani ,  Douglas Ward Thomas

IPC: H05K3/46 ,  H05K3/00 ,  H05K1/14 ,  H05K3/40 ,  H05K1/11 ,  H05K3/10

CPC classification number: H01H85/12 ,  H01H85/0013 ,  H01H85/055 ,  H01H85/06 ,  H01H85/143 ,  H01H85/20 ,  H01H85/306 ,  H01H85/56 ,  H01H2001/5877 ,  H01H2085/025 ,  H01H2085/0555 ,  H05K1/115 ,  H05K1/144 ,  H05K3/0047 ,  H05K3/06 ,  H05K3/108 ,  H05K3/4076 ,  H05K3/462 ,  H05K3/4623 ,  H05K3/4638 ,  H05K2201/0338 ,  H05K2201/041 ,  H05K2201/09227 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K2203/1438 ,  H05K2203/166 ,  Y10T29/49165

Abstract: A method of making printed circuit board vias using a double drilling and plating method is disclosed. A first hole is drilled in a core, the first hole having a first diameter. The first hole is filled and/or plated with an electrically conductive material. A circuit pattern may be formed on one or two conductive layers of the core. A multilayer structure may then be formed including a plurality of cores that also include pre-drilled and plated via holes, wherein at least some of the pre-drilled and plated via holes are aligned with the first hole. A second hole is then drilled within the first hole and the aligned pre-drilled and plated holes, the second hole having a second diameter where the second diameter is smaller than the first diameter. A conductive material is then plated to an inner surface of the second hole.

公开(公告)号：US20140262455A1

公开(公告)日：2014-09-18

申请号：US14205331

申请日：2014-03-11

Applicant: SANMINA CORPORATION

Inventor： Shinichi Iketani ,  Dale Kersten

IPC: H05K1/11 ,  H05K1/02

CPC classification number: H05K3/429 ,  H05K1/0251 ,  H05K1/115 ,  H05K2201/0187 ,  H05K2201/09536 ,  H05K2201/09645 ,  H05K2203/061 ,  H05K2203/0713 ,  Y10T29/49165

Abstract: A multilayer printed circuit board is provided having a first dielectric layer and a first plating resist selectively positioned in the first dielectric layer. A second plating resist may be selectively positioned in the first dielectric layer or a second dielectric layer, the second plating resist separate from the first plating resist. A through hole extends through the first dielectric layer, the first plating resist, and the second plating resist. An interior surface of the through hole is plated with a conductive material except along a length between the first plating resist and the second plating resist. This forms a partitioned plated through hole having a first via segment electrically isolated from a second via segment.