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公开(公告)号：US20130335056A1
公开(公告)日：2013-12-19
申请号：US13908121
申请日：2013-06-03
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Hiroki INOUE , Kiyoshi KATO , Shuhei NAGATSUKA , Koichiro KAMATA , Tsutomu MURAKAWA , Takahiro TSUJI , Kaori IKADA
IPC: G05F3/16
Abstract: One object of the present invention is to provide a regulator circuit with an improved noise margin. In a regulator circuit including a bias circuit generating a reference voltage on the basis of the potential difference between a first power supply terminal and a second power supply terminal, and a voltage regulator outputting a potential to an output terminal on the basis of a reference potential input from the bias circuit, a bypass capacitor is provided between a power supply terminal and a node to which a gate of a transistor included in the bias circuit is connected.
Abstract translation: 本发明的一个目的是提供一种具有改善的噪声容限的调节器电路。 在包括基于第一电源端子和第二电源端子之间的电位差产生参考电压的偏置电路的调节器电路中，以及基于参考电位向输出端子输出电位的电压调节器 在偏置电路的输入端，在电源端子与偏置电路中包含的晶体管的栅极连接的节点之间设置有旁路电容器。
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公开(公告)号：US20250141355A1
公开(公告)日：2025-05-01
申请号：US18986896
申请日：2024-12-19
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Hiroki INOUE , Kousuke SASAKI , Yuto YAKUBO , Kei TAKAHASHI
Abstract: A novel oscillator, an amplifier circuit, an inverter circuit, an amplifier circuit, a battery control circuit, a battery protection circuit, a power storage device, a semiconductor device, an electric device, and the like are provided. The semiconductor device includes an oscillator including a first transistor containing a metal oxide, and a second transistor to a fifth transistor, in which a first potential is supplied to a gate of the second transistor and a gate of the third transistor when the first transistor is turned on, and the first potential is held when the first transistor is turned off. The oscillator supplies a first signal based on the first potential to a first circuit. The first circuit performs at least one of shaping and amplification on the first signal. The second transistor and the fourth transistor are connected in series, and the third transistor and the fifth transistor are connected in series. A source or a drain of the third transistor is electrically connected to a gate of the fourth transistor, and a source or a drain of the fourth transistor is electrically connected to the gate of the third transistor.
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公开(公告)号：US20240305909A1
公开(公告)日：2024-09-12
申请号：US18668606
申请日：2024-05-20
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Takeya HIROSE , Seiichi YONEDA , Hiroki INOUE , Takayuki IKEDA , Shunpei YAMAZAKI
IPC: H04N25/705 , H04N25/77 , H04N25/78
CPC classification number: H04N25/705 , H04N25/77 , H04N25/78
Abstract: An imaging device having a function of processing an image is provided. The imaging device has an additional function such as image processing, can hold analog data obtained by an image capturing operation in a pixel, and can extract data obtained by multiplying the analog data by a predetermined weight coefficient. Difference data between adjacent light-receiving devices can be obtained in a pixel, and data on luminance gradient can be obtained. When the data is taken in a neural network or the like, inference of distance data or the like can be performed. Since enormous volume of image data in the state of analog data can be held in pixels, processing can be performed efficiently.
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公开(公告)号：US20240268096A1
公开(公告)日：2024-08-08
申请号：US18423850
申请日：2024-01-26
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Yuki OKAMOTO , Takanori MATSUZAKI , Hiroki INOUE
IPC: H10B12/00
Abstract: A memory device capable of reading multi-bit data at a time is provided. The memory device includes a first layer and a second layer positioned above or below the first layer. The first layer includes a first transistor and a first capacitor, and the second layer includes a second transistor and a second capacitor. Each of the first and second capacitors is a trench capacitor, and the trench length of the second capacitor is larger than the trench length of the first capacitor. A voltage retained in the first capacitor corresponds to a lower bit signal of data, and a voltage retained in the second capacitor corresponds to a higher bit signal of the data.
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公开(公告)号：US20220279140A1
公开(公告)日：2022-09-01
申请号：US17630074
申请日：2020-07-28
Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Inventor： Seiichi YONEDA , Hiromichi GODO , Yusuke NEGORO , Hiroki INOUE , Takahiro FUKUTOME
Abstract: An imaging device with a novel structure is provided. The imaging device includes an imaging region provided with a plurality of pixels. The plurality of pixels included in the imaging region include a first pixel and a second pixel. The imaging device has a function of selecting a first region or a second region. The first region includes the same number of pixels as the second region. The first region includes at least the first and second pixels. The second region includes at least the second pixel. The pixels included in the first region or the second region have a function of outputting imaging signals obtained by the pixels. The imaging device generates first image data by concurrently reading the imaging signals output from the pixels included in the first region and performing arithmetic operation on the signals. The imaging device generates second image data by concurrently reading the imaging signals output from the pixels included in the second region and performing arithmetic operation on the signals. A first conceptual image can be generated with the use of the first image data and the second image data.
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Patent Agency Ranking
公开(公告)号：US20220173737A1
公开(公告)日：2022-06-02
申请号：US17441804
申请日：2020-03-12
Applicant: Semiconductor Energy Laboratory Co., Ltd
Inventor： Hiroki INOUE , Munehiro KOZUMA , Takeshi AOKI , Shuji FUKAI , Fumika AKASAWA , Sho NAGAO
Abstract: A semiconductor device is provided; the semiconductor device includes unipolar transistors. A steady-state current does not flow in the semiconductor device. The semiconductor device uses a high-level potential and a low-level potential to express a high level and a low level, respectively. The semiconductor device includes unipolar transistors, a capacitor, first and second input terminals, and an output terminal. To the second input terminal, a signal is input whose logic is inverted from the logic of a signal input to the first input terminal. The semiconductor device has a circuit structure called bootstrap in which two unipolar transistors are connected in series between the high-level potential and the low-level potential and a capacitor is provided between an output terminal and a gate of one of the two transistors. A delay is caused between the gate of the transistor and the signal output from the output terminal, whereby the bootstrap can be certainly performed.
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公开(公告)号：US20220172677A1
公开(公告)日：2022-06-02
申请号：US17546696
申请日：2021-12-09
Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Inventor： Shintaro HARADA , Yoshiyuki KUROKAWA , Takeshi AOKI , Yuki OKAMOTO , Hiroki INOUE , Koji KUSUNOKI , Yosuke TSUKAMOTO , Katsuki YANAGAWA , Kei TAKAHASHI , Shunpei YAMAZAKI
Abstract: An electronic device capable of efficiently recognizing a handwritten character is provided.
The electronic device includes a first circuit, a display portion, and a touch sensor. The first circuit includes a neural network. The display portion includes a flexible display. The touch sensor has the function of outputting an input handwritten character as image information to the first circuit. The first circuit has the function of analyzing the image information and converting the image information into character information, and a function of displaying an image including the character information on the display portion. The analysis is performed by inference through the use of the neural network.-
公开(公告)号：US20220085427A1
公开(公告)日：2022-03-17
申请号：US17420536
申请日：2020-01-06
Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Inventor： Ryota TAJIMA , Kei TAKAHASHI , Hiroki INOUE , Munehiro KOZUMA , Takahiro FUKUTOME
IPC: H01M10/44 , G01R31/367 , H02J7/00 , H01M10/48
Abstract: A semiconductor device that inhibits deterioration of a secondary battery is provided. The semiconductor device includes a secondary battery module and a first circuit. The secondary battery module includes a secondary battery and a sensor. The first circuit includes a variable resistor. The sensor has a function of measuring a temperature of the secondary battery. The first circuit has a function of judging the charge voltage of the secondary battery and outputting a first result; a function of judging the temperature of the secondary battery measured by the sensor and outputting a second result; a function of determining the magnitude of the variable resistor on the basis of the first result and the second result; a function of discharging the charge voltage through the variable resistor; and a function of stopping discharge when the charge voltage reaches a specified voltage.
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公开(公告)号：US20220006309A1
公开(公告)日：2022-01-06
申请号：US17292218
申请日：2019-11-12
Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Inventor： Kei TAKAHASHI , Yuki OKAMOTO , Minato ITO , Takahiko ISHIZU , Hiroki INOUE , Shunpei YAMAZAKI
IPC: H02J7/00 , H01M10/44 , H03K17/082 , H01M10/42 , H03K3/0231
Abstract: A semiconductor device with reduced power consumption is provided. The semiconductor device includes a node ND1, a node ND2, a resistor, a capacitor, and a comparison circuit. The resistor is electrically connected in series between one of a positive electrode and a negative electrode of a secondary battery and a first terminal. The resistor has a function of converting current flowing between the one of the positive electrode and the negative electrode of the secondary battery and the first terminal into a first voltage. The first voltage is added to a voltage of the node ND2 through the capacitor. The comparison circuit has a function of comparing a voltage of the node ND1 and the voltage of the node ND2. The comparison circuit outputs a signal that notifies detection of overcurrent when the voltage of the node ND2 is higher than the voltage of the node ND1.
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公开(公告)号：US20210384751A1
公开(公告)日：2021-12-09
申请号：US17286088
申请日：2019-10-16
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Kei TAKAHASHI , Takayuki IKEDA , Takanori MATSUZAKI , Munehiro KOZUMA , Hiroki INOUE , Ryota TAJIMA , Yohei MOMMA , Mayumi MIKAMI , Kazutaka KURIKI , Shunpei YAMAZAKI
IPC: H02J7/00
Abstract: A battery control circuit with a novel structure, a battery protection circuit with a novel structure, and a power storage device including either of the battery circuits are provided. The power storage device includes a first circuit portion, a second circuit portion, a third circuit portion, and a secondary battery; the first circuit portion has a function of controlling charging of the secondary battery; the first circuit portion has a function of supplying the start time and the end time of the charging of the secondary battery to the third circuit portion; the second circuit portion has functions of generating a first voltage and a first current and supplying them to the third circuit portion; the third circuit portion has a function of generating a second voltage by charging the first current in a capacitor; and the third circuit portion has a function of comparing the first voltage and the second voltage.
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