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公开(公告)号：US20170104132A1
公开(公告)日：2017-04-13
申请号：US15391922
申请日：2016-12-28
Applicant: Sensor Electronic Technology, Inc.
Inventor： Rakesh Jain , Wenhong Sun , Jinwei Yang , Maxim S. Shatalov , Alexander Dobrinsky , Remigijus Gaska , Michael Shur
CPC classification number: H01L33/32 , H01L21/0237 , H01L21/02458 , H01L21/02507 , H01L21/0254 , H01L21/0262 , H01L29/151 , H01L33/007 , H01L33/0075 , H01L33/025 , H01L33/04 , H01L33/06 , H01L33/12 , H01L33/20
Abstract: A solution for fabricating a semiconductor structure is provided. The semiconductor structure includes a plurality of semiconductor layers grown over a substrate using a set of epitaxial growth periods. During each epitaxial growth period, a first semiconductor layer having one of: a tensile stress or a compressive stress is grown followed by growth of a second semiconductor layer having the other of: the tensile stress or the compressive stress directly on the first semiconductor layer.
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公开(公告)号：US20170104129A1
公开(公告)日：2017-04-13
申请号：US15389479
申请日：2016-12-23
Applicant: Sensor Electronic Technology, Inc.
Inventor： Rakesh Jain , Wenhong Sun , Jinwei Yang , Maxim S. Shatalov , Alexander Dobrinsky , Michael Shur , Remigijus Gaska
CPC classification number: H01L33/06 , H01L21/0242 , H01L21/0243 , H01L21/02458 , H01L21/0254 , H01L21/02639 , H01L21/0265 , H01L29/2003 , H01L29/518 , H01L29/7786 , H01L33/12 , H01L33/22 , H01L33/24 , H01L33/32 , H01L2933/0083 , H01L2933/0091
Abstract: A device having a layer with a patterned surface for improving the growth of semiconductor layers, such as group III nitride-based semiconductor layers with a high concentration of aluminum, is provided. The patterned surface can include a substantially flat top surface and a plurality of stress reducing regions, such as openings. The substantially flat top surface can have a root mean square roughness less than approximately 0.5 nanometers, and the stress reducing regions can have a characteristic size between approximately 0.1 microns and approximately five microns and a depth of at least 0.2 microns. A layer of group-III nitride material can be grown on the first layer and have a thickness at least twice the characteristic size of the stress reducing regions.
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33.发明授权Device with transparent and higher conductive regions in lateral cross section of semiconductor layer 有权具有透明和较高导电区域的器件在半导体层的横截面中公开(公告)号：US09595634B2
公开(公告)日：2017-03-14
申请号：US15200313
申请日：2016-07-01
Applicant: Sensor Electronic Technology, Inc.
Inventor： Michael Shur , Maxim S. Shatalov , Alexander Dobrinsky , Remigijus Gaska , Jinwei Yang
IPC: H01L33/06 , H01L33/00 , H01L33/32 , H01L33/22 , H01S5/343 , H01L33/10 , H01S5/125 , H01S5/30 , B82Y10/00 , H01L21/02 , H01L29/15 , H01L29/778 , H01L29/20
CPC classification number: H01L33/06 , B82Y10/00 , B82Y20/00 , H01L21/02458 , H01L21/02507 , H01L21/0254 , H01L29/15 , H01L29/2003 , H01L29/778 , H01L33/0025 , H01L33/10 , H01L33/22 , H01L33/32 , H01L33/325 , H01L33/405 , H01S5/125 , H01S5/3054 , H01S5/3063 , H01S5/343 , H01S5/34333 , H01S5/34346
Abstract: A device including one or more layers with lateral regions configured to facilitate the transmission of radiation through the layer and lateral regions configured to facilitate current flow through the layer is provided. The layer can comprise a short period superlattice, which includes barriers alternating with wells. In this case, the barriers can include both transparent regions, which are configured to reduce an amount of radiation that is absorbed in the layer, and higher conductive regions, which are configured to keep the voltage drop across the layer within a desired range.
Abstract translation: 提供了一种包括一个或多个具有横向区域的层，该层被配置为有助于辐射通过该层的传输和被配置为促进流过该层的电流的横向区域。 该层可以包括短期超晶格，其包括与井交替的障碍物。 在这种情况下，障碍物可以包括被配置为减少在层中吸收的辐射量的透明区域以及被配置为将跨越层的电压降保持在期望范围内的较高导电区域。
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公开(公告)号：US20160343901A1
公开(公告)日：2016-11-24
申请号：US15225382
申请日：2016-08-01
Applicant: Sensor Electronic Technology, Inc.
Inventor： Michael Shur , Rakesh Jain , Maxim S. Shatalov , Alexander Dobrinsky , Jinwei Yang , Remigijus Gaska , Mikhail Gaevski
CPC classification number: H01L33/06 , H01L33/007 , H01L33/18 , H01L33/30 , H01L33/382 , H01L2224/14 , H01S5/0224 , H01S5/3209 , H01S5/3413 , H01S5/34333
Abstract: A device comprising a semiconductor layer including a plurality of compositional inhomogeneous regions is provided. The difference between an average band gap for the plurality of compositional inhomogeneous regions and an average band gap for a remaining portion of the semiconductor layer can be at least thermal energy. Additionally, a characteristic size of the plurality of compositional inhomogeneous regions can be smaller than an inverse of a dislocation density for the semiconductor layer.
Abstract translation: 提供了包括包括多个组成不均匀区域的半导体层的器件。 多个组成不均匀区域的平均带隙与半导体层的剩余部分的平均带隙之间的差可以是至少热能。 此外，多个组成不均匀区域的特征尺寸可以小于半导体层的位错密度的倒数。
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公开(公告)号：US09502509B2
公开(公告)日：2016-11-22
申请号：US15083423
申请日：2016-03-29
Applicant: Sensor Electronic Technology, Inc.
Inventor： Maxim S. Shatalov , Jinwei Yang , Wenhong Sun , Rakesh Jain , Michael Shur , Remigijus Gaska
IPC: H01L31/00 , H01L29/15 , H01L29/205 , H01L29/20 , H01L29/06
CPC classification number: H01L29/158 , H01L21/0237 , H01L21/02458 , H01L21/02505 , H01L21/02507 , H01L21/02513 , H01L21/0254 , H01L21/0262 , H01L21/02639 , H01L21/0265 , H01L29/0657 , H01L29/2003 , H01L29/205 , H01L33/007 , H01L33/12
Abstract: A semiconductor structure, such as a group III nitride-based semiconductor structure is provided. The semiconductor structure includes a cavity containing semiconductor layer. The cavity containing semiconductor layer can have a thickness greater than two monolayers and a multiple cavities. The cavities can have a characteristic size of at least one nanometer and a characteristic separation of at least five nanometers.
Abstract translation: 提供了诸如III族氮化物基半导体结构的半导体结构。 半导体结构包括含有半导体层的空腔。 含腔的半导体层可以具有大于两个单层和多个空腔的厚度。 空腔可以具有至少一纳米的特征尺寸和至少五纳米的特征分离。
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Patent Agency Ranking
公开(公告)号：US20160260867A1
公开(公告)日：2016-09-08
申请号：US15069272
申请日：2016-03-14
Applicant: Sensor Electronic Technology, Inc.
Inventor： Maxim S. Shatalov , Remigijus Gaska , Jinwei Yang , Michael Shur , Alexander Dobrinsky
CPC classification number: H01L33/06 , B82Y10/00 , B82Y20/00 , H01L29/15 , H01L29/155 , H01L29/2003 , H01L29/201 , H01L29/207 , H01L33/0075 , H01L33/04 , H01L33/145 , H01L33/32 , H01L33/325 , H01S5/2009 , H01S5/3211 , H01S5/3216 , H01S5/3407 , H01S5/34333
Abstract: A solution for designing and/or fabricating a structure including a quantum well and an adjacent barrier is provided. A target band discontinuity between the quantum well and the adjacent barrier is selected to coincide with an activation energy of a dopant for the quantum well and/or barrier. For example, a target valence band discontinuity can be selected such that a dopant energy level of a dopant in the adjacent barrier coincides with a valence energy band edge for the quantum well and/or a ground state energy for free carriers in a valence energy band for the quantum well. Additionally, a target doping level for the quantum well and/or adjacent barrier can be selected to facilitate a real space transfer of holes across the barrier. The quantum well and the adjacent barrier can be formed such that the actual band discontinuity and/or actual doping level(s) correspond to the relevant target(s).
Abstract translation: 提供了一种用于设计和/或制造包括量子阱和相邻屏障的结构的解决方案。 选择量子阱和相邻屏障之间的目标频带不连续性以与量子阱和/或屏障的掺杂剂的活化能一致。 例如，可以选择目标价带不连续性，使得相邻势垒中的掺杂剂的掺杂剂能级与量子阱的价态能带边缘和/或价态能带中的自由载流子的基态能量一致 量子阱。 另外，可以选择量子阱和/或相邻势垒的目标掺杂水平以促进穿过势垒的空穴的实际空间传递。 可以形成量子阱和相邻势垒，使得实际的带不连续性和/或实际掺杂水平对应于相关目标。
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公开(公告)号：US09412902B2
公开(公告)日：2016-08-09
申请号：US14628281
申请日：2015-02-22
Applicant: Sensor Electronic Technology, Inc.
Inventor： Maxim S. Shatalov , Jinwei Yang , Alexander Dobrinsky , Michael Shur , Remigijus Gaska
CPC classification number: H01L33/12 , G06F17/505 , H01L33/0025 , H01L33/007 , H01L33/0075 , H01L33/06 , H01L33/145 , H01L33/24 , H01L33/32 , H01L33/38 , H01L33/46
Abstract: A semiconductor structure comprising a buffer structure and a set of semiconductor layers formed adjacent to a first side of the buffer structure is provided. The buffer structure can have an effective lattice constant and a thickness such that an overall stress in the set of semiconductor layers at room temperature is compressive and is in a range between approximately 0.1 GPa and 2.0 GPa. The buffer structure can be grown using a set of growth parameters selected to achieve the target effective lattice constant a, control stresses present during growth of the buffer structure, and/or control stresses present after the semiconductor structure has cooled.
Abstract translation: 提供一种半导体结构，包括缓冲结构和与缓冲结构的第一侧相邻形成的一组半导体层。 缓冲结构可以具有有效的晶格常数和厚度，使得该组半导体层在室温下的总应力是压缩的，并且在约0.1GPa和2.0GPa之间的范围内。 可以使用选择的一组生长参数来生长缓冲结构，以实现目标有效晶格常数a，缓冲结构生长期间存在的控制应力和/或半导体结构冷却后存在的控制应力。
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公开(公告)号：US09324560B2
公开(公告)日：2016-04-26
申请号：US14660125
申请日：2015-03-17
Applicant: Sensor Electronic Technology, Inc.
Inventor： Maxim S. Shatalov , Rakesh Jain , Jinwei Yang , Michael Shur , Remigijus Gaska
CPC classification number: H01L33/22 , G06F17/5068 , G06F2217/12 , H01L21/0237 , H01L21/0242 , H01L21/0243 , H01L21/02458 , H01L21/0254 , H01L21/02617 , H01L21/02639 , H01L21/0265 , H01L33/007 , H01L33/0075 , H01L33/06 , H01L33/12 , H01L33/32 , H01L2224/16225
Abstract: A patterned surface for improving the growth of semiconductor layers, such as group III nitride-based semiconductor layers, is provided. The patterned surface can include a set of substantially flat top surfaces and a plurality of openings. Each substantially flat top surface can have a root mean square roughness less than approximately 0.5 nanometers, and the openings can have a characteristic size between approximately 0.1 micron and five microns. One or more of the substantially flat top surfaces can be patterned based on target radiation.
Abstract translation: 提供了用于改善半导体层的生长的图案化表面，例如III族氮化物基半导体层。 图案化表面可以包括一组基本平坦的顶表面和多个开口。 每个基本上平坦的顶表面可以具有小于约0.5纳米的均方根粗糙度，并且开口可以具有在约0.1微米和5微米之间的特征尺寸。 基本平坦的顶表面中的一个或多个可以基于目标辐射进行图案化。
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公开(公告)号：US20160104784A1
公开(公告)日：2016-04-14
申请号：US14973563
申请日：2015-12-17
Applicant: Sensor Electronic Technology, Inc.
Inventor： Remigijus Gaska , Michael Shur , Jinwei Yang , Alexander Dobrinsky , Maxim S. Shatalov
IPC: H01L29/45 , H01L29/15 , H01L29/20 , H01L33/40 , H01L29/737 , H01L33/06 , H01L33/14 , H01L33/32 , H01L21/285 , H01L29/205
CPC classification number: H01L29/452 , H01L21/28575 , H01L29/155 , H01L29/2003 , H01L29/201 , H01L29/205 , H01L29/401 , H01L29/66431 , H01L29/66462 , H01L29/737 , H01L29/778 , H01L29/7786 , H01L33/007 , H01L33/0075 , H01L33/06 , H01L33/14 , H01L33/32 , H01L33/40 , H01L33/405 , H01L2933/0016
Abstract: A solution for forming an ohmic contact to a semiconductor layer is provided. A masking material is applied to a set of contact regions on the surface of the semiconductor layer. Subsequently, one or more layers of a device heterostructure are formed on the non-masked region(s) of the semiconductor layer. The ohmic contact can be formed after the one or more layers of the device heterostructure are formed. The ohmic contact formation can be performed at a processing temperature lower than a temperature range within which a quality of a material forming any semiconductor layer in the device heterostructure is damaged.
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公开(公告)号：US20150243841A1
公开(公告)日：2015-08-27
申请号：US14628281
申请日：2015-02-22
Applicant: Sensor Electronic Technology, Inc.
Inventor： Maxim S. Shatalov , Jinwei Yang , Alexander Dobrinsky , Michael Shur , Remigijus Gaska
CPC classification number: H01L33/12 , G06F17/505 , H01L33/0025 , H01L33/007 , H01L33/0075 , H01L33/06 , H01L33/145 , H01L33/24 , H01L33/32 , H01L33/38 , H01L33/46
Abstract: A semiconductor structure comprising a buffer structure and a set of semiconductor layers formed adjacent to a first side of the buffer structure is provided. The buffer structure can have an effective lattice constant and a thickness such that an overall stress in the set of semiconductor layers at room temperature is compressive and is in a range between approximately 0.1 GPa and 2.0 GPa. The buffer structure can be grown using a set of growth parameters selected to achieve the target effective lattice constant a, control stresses present during growth of the buffer structure, and/or control stresses present after the semiconductor structure has cooled.
Abstract translation: 提供一种半导体结构，包括缓冲结构和与缓冲结构的第一侧相邻形成的一组半导体层。 缓冲结构可以具有有效的晶格常数和厚度，使得该组半导体层在室温下的总应力是压缩的，并且在约0.1GPa和2.0GPa之间的范围内。 可以使用选择的一组生长参数来生长缓冲结构，以实现目标有效晶格常数a，缓冲结构生长期间存在的控制应力和/或半导体结构冷却后存在的控制应力。
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